In examples, an electronic device comprises a printed circuit board (PCB), an orifice extending through the PCB, and a semiconductor die suspended above the orifice by aluminum bond wires. The semiconductor die is vertically aligned with the orifice and the bond wires coupled to the PCB.

According to one embodiment, a semiconductor device includes a first container and a second container. The second container is inside the first container. A semiconductor element is inside the second container. The second container is formed of a lower portion, a side portion fixed to the lower portion, and an upper portion fixed to the side portion and the first container. The side portion is a first metal material covered with a first insulator. The lower portion and the side portion of the second container are spaced from the first container. The semiconductor device may be used as a power module or the like in some instances, and the semiconductor element may be one or more transistors of the like.

A power semiconductor module arrangement includes a housing, at least one substrate arranged inside the housing and including a dielectric insulation layer and a first metallization layer arranged on a first side of the dielectric insulation layer, and a heat sink or base plate. The housing includes sidewalls and a cover and is attached to the heat sink or base plate. The sidewalls exert pressure on the at least one substrate such that the at least one substrate is pressed onto the heat sink or base plate. The cover exerts pressure on the sidewalls such that the sidewalls are pressed onto the at least one substrate. The housing further includes at least one press-on element arranged between and directly adjoining the sidewalls and the cover, wherein each of the at least one press-on element is compressed by the pressure that is exerted on the sidewalls by the cover.

The present disclosure provides a semiconductor package structure and a method of manufacturing the same. The semiconductor package structure includes a substrate, a first electronic component, an interlayer, a third electronic component and an encapsulant. The first electronic component is disposed on the substrate. The first electronic component has an upper surface and a lateral surface and a first edge between the upper surface and the lateral surface. The interlayer is on the upper surface of the first electronic component. The third electronic component is attached to the upper surface of the first electronic component via the interlayer. The encapsulant encapsulates the first electronic component and the interlayer. The interlayer does not contact the lateral surface of the first electronic component.

An embedded chip package according to an embodiment of the present application may include at least one chip and a frame surrounding the at least one chip, the chip having a terminal face and a back face separated by a height of the chip, the frame having a height equal to or larger than the height of the chip, wherein the gap between the chip and the frame is fully filled with a photosensitive polymer dielectric, the terminal face of the chip being coplanar with the frame, a first wiring layer being formed on the terminal face of the chip and a second wiring layer being formed on the back face of the chip.

This disclosure describes an electronic component with a package body which comprises a set of sidewalls and a bottom wall. One or more chip mounting elements extend into the space within the package from the inner surface of at least one sidewall, and at least one electronic chip is attached to the chip mounting elements. The electronic component also comprises one or more stiffening elements which extend inside the space within the package from the inner surface of one of the sidewalls to the outer surface of the bottom wall. These stiffening elements are separated from the one or more chip mounting elements inside the enclosed inner space.

An integrated circuit package can contain a semiconductor die and provide electrical connections between the semiconductor die and additional electronic components. The integrated circuit package can reduce stress placed on the semiconductor die due to movement of the integrated circuit package due to, for example, temperature changes and/or moisture levels. The integrated circuit package can at least partially mechanically isolate the semiconductor die from the integrated circuit package.

A chip device is provided. The chip device includes a substrate, at least one chip, a sealing component, a heat-conducting medium, a barrier, and a heat dissipation device. The at least one chip is disposed over a first surface of the substrate and has a heat transfer surface. The sealing component covers the at least one chip and has a heat transfer area thermal contacting the heat transfer surface of the at least one chip. The heat-conducting medium is disposed over the heat transfer area of the sealing component. The barrier is disposed around and blocks the heat-conducting medium. The heat dissipation device is disposed over the heat transfer area of the sealing component and on the heat-conducting medium. The chip device can block the heat-conducting medium through the barrier to prevent the heat-conducting medium from overflowing or losing between the sealing component and the heat dissipation device.

A heat spreading lid including a lid body and a wing portion having a thermal interface material disposed on the wing portion such that the wing portion flexibly moves with the thermal interface material independently from the lid body.

In examples, an electronic device comprises a printed circuit board (PCB), an orifice extending through the PCB, and a semiconductor die suspended above the orifice by aluminum bond wires. The semiconductor die is vertically aligned with the orifice and the bond wires coupled to the PCB.