Patent classifications
H01L23/29
ELECTRONIC COMPONENT WITH MOULDED PACKAGE
An electronic component comprising a plastic package and an electric chip which is inside the package. The electronic component comprises a metallic die pad and a metallic first support structure extends from the die pad to a first support point on one of the side surfaces of the plastic package. The electronic component also comprises a metallic opposing pad and a metallic second support structure which extends from the opposing pad to a second support point on one of the side surfaces of the plastic package.
Sintering method using a sacrificial layer on the backside metallization of a semiconductor die
An electronic device comprises a semiconductor die, a layer stack disposed on the semiconductor die and comprising one or more functional layers, wherein the layer stack comprises a protection layer which is an outermost functional layer of the layer stack, and a sacrificial layer disposed on the protection layer, wherein the sacrificial layer comprises a material which decomposes or becomes volatile at a temperature between 100° and 400° C.
Method for producing semiconductor device and intermediate for semiconductor device
This method for producing a semiconductor device comprises: a first step wherein a plurality of semiconductor chips are affixed onto a supporting substrate such that circuit surfaces of the semiconductor chips face the supporting substrate; a second step wherein a plurality of sealed layers are formed at intervals by applying the sealing resin onto the semiconductor chips by three-dimensional modeling method, each sealed layer containing one or more semiconductor chips embedded in a sealing resin; a third step wherein the sealed layers are cured or solidified; and a fourth step wherein sealed bodies are obtained by separating the cured or solidified sealed layers from the supporting substrate.
Composition for curable resin, cured product of said composition, production method for said composition and said cured product, and semiconductor device
The invention relates to a curable resin composition containing (A) a multifunctional benzoxazine compound having two or more benzoxazine rings, (B) an epoxy compound having at least one norbornane structure and at least two epoxy groups, (C) a biphenyl type epoxy compound, and (D) a curing agent, and optionally (E) an inorganic filler and (F) a curing accelerator; a cured product thereof; methods of producing the curable resin composition and the cured product; and a semiconductor device in which a semiconductor element is disposed in a cured product obtained by curing a curable resin composition containing components (A) to (D), and optionally components (E) and (F).
Composition for curable resin, cured product of said composition, production method for said composition and said cured product, and semiconductor device
The invention relates to a curable resin composition containing (A) a multifunctional benzoxazine compound having two or more benzoxazine rings, (B) an epoxy compound having at least one norbornane structure and at least two epoxy groups, (C) a biphenyl type epoxy compound, and (D) a curing agent, and optionally (E) an inorganic filler and (F) a curing accelerator; a cured product thereof; methods of producing the curable resin composition and the cured product; and a semiconductor device in which a semiconductor element is disposed in a cured product obtained by curing a curable resin composition containing components (A) to (D), and optionally components (E) and (F).
Selective thermal annealing method
A semiconductor body having a base carrier portion and a type III-nitride semiconductor portion is provided. The type III-nitride semiconductor portion includes a heterojunction and two-dimensional charge carrier gas. One or more ohmic contacts are formed in the type III-nitride semiconductor portion, the ohmic contacts forming an ohmic connection with the two-dimensional charge carrier gas. A gate structure is configured to control a conductive state of the two-dimensional charge carrier gas. Forming the one or more ohmic contacts comprises forming a structured laser-reflective mask on the upper surface of the type III-nitride semiconductor portion, implanting dopant atoms into the upper surface of the type III-nitride semiconductor portion, and performing a laser thermal anneal that activates the implanted dopant atoms.
Semiconductor device with a dielectric between portions
A semiconductor device having a channel between active sections or portions of the device is disclosed. An elastic material, such as dielectric or a polymer, is deposited into the channel and cured to increase flexibility and thermal expansion properties of the semiconductor device. The elastic material reduces the thermal and mechanical mismatch between the semiconductor device and the substrate to which the semiconductor device is coupled in downstream processing to improve reliability. The semiconductor device may also include a plurality of channels formed transverse with respect to each other. Some of the channels extend all the way through the semiconductor device, while other channels extend only partially through the semiconductor device.
PACKAGING STRUCTURE, ELECTRONIC DEVICE, AND CHIP PACKAGING METHOD
A chip is mounted on a surface of the substrate, and the thermally conductive cover is disposed on a side that is of the chip and that is away from the substrate. There is a filling area on a surface that is of the thermally conductive cover and that faces the substrate, and the filling area is opposite to the chip. There is an accommodation cavity whose opening faces the substrate in the filling area. A thermal interface material layer is filled between the chip and a bottom surface of the accommodation cavity. Between an opening edge of the accommodation cavity and the substrate, there is a first gap connected to the accommodation cavity. The filling material encircles a side surface of the thermal interface material layer, so that the filling material separates the side surface of the thermal interface material layer from air.
PASSIVATION LAYER FOR PROTECTING SEMICONDUCTOR STRUCTURES
A method for making a semiconductor structure includes forming a first fin and a second fin over a substrate. The method includes forming one or more work function layers over the first and second fins. The method includes forming a nitride-based metal film over the one or more work function layers. The method includes covering the first fin with a patternable layer. The method includes removing a second portion of the nitride-based metal film from the second fin, while leaving a first portion of the nitride-based metal film over the first fin substantially intact.
SILICON FRAGMENT DEFECT REDUCTION IN GRINDING PROCESS
A method is provided for fabricating a semiconductor wafer having a device side, a back side opposite the device side and an outer periphery edge. Suitably, the method includes: forming a top conducting layer on the device side of the semiconductor wafer; forming a passivation layer over the top conducting layer, the passivation layer being formed so as not to extend to the outer periphery edge of the semiconductor wafer; and forming a protective layer over the passivation layer, the protective layer being spin coated over the passivation layer so as to have a smooth top surface at least in a region proximate to the outer periphery edge of the semiconductor wafer.