A method is disclosed for producing a power semiconductor module that includes a substrate, at least one semiconductor body, a connecting element and a contact element. The method includes: arranging the substrate in a housing having walls; at least partly filling a capacity formed by the walls of the housing and the substrate with an encapsulation material; hardening the encapsulation material to form a hard encapsulation; and closing the housing, wherein the contact element extends from the connecting element through an interior of the housing and through an opening in a cover of the housing to an outside of the housing in a direction perpendicular to a first surface of a first metallization layer of the substrate.

The present invention relates to an electronic module. In particular, to an electronic module which includes one or more components embedded in an installation base. The electronic module can be a module like a circuit board, which includes several components, which are connected to each other electrically, through conducting structures manufactured in the module. The components can be passive components, microcircuits, semiconductor components, or other similar components. Components that are typically connected to a circuit board form one group of components. Another important group of components are components that are typically packaged for connection to a circuit board. The electronic modules to which the invention relates can, of course, also include other types of components.

A method of manufacture for a semiconductor package includes; forming a first wiring structure, connecting a semiconductor chip to the first wiring structure, forming a lower encapsulant on the first wiring structure to cover at least a portion of a lateral surface of the semiconductor chip, wherein the lower encapsulant does not cover an upper surface of the semiconductor chip, forming an upper encapsulant on the lower encapsulant, wherein the upper encapsulant covers the upper surface of the semiconductor chip and the upper encapsulant has a materially different composition than the lower encapsulant, and forming a second wiring structure on the upper encapsulant.

A semiconductor package includes a package substrate, at least one semiconductor chip mounted on the package substrate, and a molding member that surrounds the at least one semiconductor chip. The molding member includes fillers. Each of the fillers includes a core and a coating layer that surrounds the core. The core includes a non-electromagnetic material and the coating layer includes an electromagnetic material. The molding member includes regions respectively have different distributions of the fillers.

A semiconductor device includes: a metal block; a semiconductor element fixed to an upper surface of the block with a first joining material; a main terminal fixed to an upper surface of the element with a second joining material; a signal terminal electrically connected to the element; and a mold resin covers the element, the first and second joining materials, a part of the block, of the main and signal terminals. In the element, a current flows in a longitudinal direction. A lower surface of the block is exposed from the resin. The main and the signal terminals are exposed from a side surface of the resin. The main terminal has a first portion in the resin, a second portion continuous with the first portion and bent downward outside the resin, and a third portion continuous with the second portion and substantially parallel to a lower surface of the resin.

A semiconductor package is provided. The semiconductor package includes: semiconductor dies, separated from one another, and including die I/Os at their active sides; and a redistribution structure, disposed at the active sides of the semiconductor dies and connected to the die I/Os, wherein the redistribution structure includes first and second routing layers sequentially arranged along a direction away from the die I/Os, the first routing layer includes a ground plane and first signal lines laterally surrounded by and isolated from the first ground plane, the first signal lines connect to the die I/Os and rout the die I/Os from a central region to a peripheral region of the redistribution structure, the second routing layer includes second signal lines and ground lines, and the second signal lines and the ground lines respectively extend from a location in the peripheral region to another location in the peripheral region through the central region.

Various embodiments of the teachings herein include a method for joining and insulating a power electronic semiconductor component with contact surfaces to a substrate. In some embodiments, the method includes: preparing the substrate with a metallization defining an installation slot having joining material, wherein the substrate comprises an organic or a ceramic wiring support; arranging an electrically insulating film and the semiconductor component on the substrate, such that the contact surfaces of the semiconductor component facing the substrate are omitted from the film and regions of the semiconductor component exposed by the contact surfaces are insulated at least in part by the film from the substrate and from the contact surfaces; and joining the semiconductor component to the substrate and electrically insulating the semiconductor component at least in part by the film in one step.

The present invention aims to provide a means by which a cured product to be obtained has a low dielectric loss tangent and higher heat resistance. Specifically, provided is an active ester resin that is a reaction product of a first aromatic compound having two or more phenolic hydroxy groups, a second aromatic compound having a phenolic hydroxy group, and a third aromatic compound having two or more carboxy groups and/or an acid halide thereof or an esterified compound thereof, in which at least one of the first aromatic compound, the second aromatic compound, and the third aromatic compound and/or the acid halide thereof or the esterified compound thereof has an unsaturated bond-containing substituent.

In an embodiment, a method includes forming a conductive feature adjacent to a substrate; treating the conductive feature with a protective material, the protective material comprising an inorganic core with an organic coating around the inorganic core, the treating the conductive feature comprising forming a protective layer over the conductive feature; and forming an encapsulant around the conductive feature and the protective layer. In another embodiment, the method further includes, before forming the encapsulant, rinsing the protective layer with water. In another embodiment, the protective layer is selectively formed over the conductive feature.

A component carrier includes a stack having at least one electrically conductive layer structure and at least one electrically insulating layer structure; a barrier structure; and a component. The component has at least one pad embedded in the stack and/or in the barrier structure. At least a portion of one of the electrically conductive layer structure and the at least one pad includes copper in contact with the barrier structure.