A semiconductor chip is arranged on a first surface of a die pad in a substrate (leadframe) including an array of electrically conductive leads. An encapsulation of laser direct structuring (LDS) material encapsulates the substrate and the semiconductor chip. The encapsulation has a first surface, a second surface opposed to the first surface and a peripheral surface. The array of electrically conductive leads protrude from the peripheral surface with areas of the second surface of the encapsulation arranged between adjacent leads. LDS structured areas of the second surface located between adjacent leads in the array of electrically conductive leads provide a further array of electrically conductive leads exposed at the second surface. First and second electrically conductive vias extending through the encapsulation material as well as electrically conductive lines over the encapsulation material provide an electrical bonding pattern between the semiconductor chip and selected ones of the leads.

A tool and method for processing substrates by encapsulating a mask to protect from degradation during an etch-back to prevent a feature liner material from pinching off an opening during deposition-etch cycles used to fabricate high aspect ratio features with very tight critical dimension control.

Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package is provided that includes a package substrate that has a first edge and a second edge opposite to the first edge. A semiconductor chip is mounted on the package substrate. A thermal interface material is positioned on the semiconductor chip. A lid is positioned over the thermal interface material. A spring biasing mechanism is included that is operable to bias the lid away from the package substrate so that the lid, when subjected to a compressive force, can translate toward the package substrate and impart a compressive force on the thermal interface material.

A semiconductor package assembly and method of manufacturing is provided. The assembly includes a semiconductor package and a moulding resin case encapsulating the semiconductor package. The package includes a lead frame having a first frame side and a second frame side opposite to the first frame side; a silicon die structure having a first die side and a second die side opposite to the first side, the silicon die structure being mounted with its second die side on the first frame side of the lead frame; one or more bond wires electrically connecting the silicon die structure with the lead frame; as well as a coating layer covering the semiconductor package from the encapsulating moulding resin case, the coating layer being composed of two or more different amorphous layer coatings. The use of a coating layer covering the complete semiconductor package forming the encapsulating moulding resin case prevents any corrosion.

Systems and methods for manufacturing flexible electronics are described herein. Methods in accordance with embodiments of the present technology can include disposing electrical features, such as thin film circuits, on a first side of a glass substrate, applying a first protective material over the electronic features, and exposing a second side of the glass substrate to a chemical etching tank to thin the glass substrate to a predetermined thickness. The thinning process can remove cracks and other defects from the second side of the glass substrate and enhance the flexibility of the electronic assembly. A second protective material can be disposed on the second side of the thinned glass substrate to maintain the enhanced backside surface of the glass substrate. In some embodiments, the method also includes singulating the plurality of electronic features into individual electronic components by submerging the electronic assembly into a chemical etching tank.

Disclosed herein is the formation of p-type transparent conducting oxides (TCO) having a structure of Mg.sub.xNi.sub.1-xO or Zn.sub.xNi.sub.1-xO. These structures disrupt the two-dimensional confinement of individual holes (the dominant charge carrier transport mechanism in pure NiO) creating three-dimensional hole transport by providing pathways for hole transfer in directions that are unfavorable in pure NiO. Forming these structures preserves NiO's transparency to visible light since the band gaps do not deviate significantly from that of pure NiO. Furthermore, forming Mg.sub.xNi.sub.1-xO or Zn.sub.xNi.sub.1-xO does not lead to hole trapping on O ions adjacent to Zn and Mg ions. The formation of these alloys will lead to creation of three-dimensional hole transport and improve NiO's conductivity for use as p-type TCO, without adversely affecting the favorable properties of pure NiO.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface with conductive contacts, in a first layer; a first material surrounding the first die and extending along a thickness of the first die from the second surface, and wherein the first material includes first particles having an average diameter between 200 and 500 nanometers; a second material surrounding the first die and extending along the thickness of the first die from the first surface, and wherein the second material includes second particles having an average diameter between 0.5 and 12 microns; an interface portion, between the first and second materials, including the first and second particles; and a second die, in a second layer on the first layer, electrically coupled to the conductive contacts on the first die.

A semiconductor device that can be embedded in a living body is provided. The semiconductor device being embeddable in a living body includes a communication portion, a control portion, a memory portion, an arithmetic portion, and a sensor portion. The control portion has a function of controlling the communication portion, the arithmetic portion, and the memory portion. The memory portion has a function of retaining identification information. The arithmetic portion has a function of using first information and second information supplied from the sensor portion to generate third information. The control portion has a function of making the arithmetic portion perform arithmetic processing in response to a signal input through the communication portion. The control portion has a function of outputting, through the communication portion to the outside, one or both of the identification information and the third information, in response to a signal input through the communication portion. The arithmetic portion preferably includes a transistor including an oxide semiconductor in a channel formation region. The semiconductor device is preferably covered with a coating material.

Systems and methods for manufacturing flexible electronics are described herein. Methods in accordance with embodiments of the present technology can include disposing electrical features, such as thin film circuits, on a first side of a glass substrate, applying a first protective material over the electronic features, and exposing a second side of the glass substrate to a chemical etching tank to thin the glass substrate to a predetermined thickness. The thinning process can remove cracks and other defects from the second side of the glass substrate and enhance the flexibility of the electronic assembly. A second protective material can be disposed on the second side of the thinned glass substrate to maintain the enhanced backside surface of the glass substrate. In some embodiments, the method also includes singulating the plurality of electronic features into individual electronic components by submerging the electronic assembly into a chemical etching tank.

A method for encapsulating a microelectronic device, arranged on a support substrate, with an encapsulation cover includes, inter alia, the following sequence of steps: a) providing a support substrate on which a microelectronic device is arranged, b) depositing a bonding layer on the first face of the substrate, around the microelectronic device, c) positioning an encapsulation cover on the bonding layer in such a way as to encapsulate the microelectronic device, d) thinning the second main face of the support substrate and the second main face of the encapsulation cover by chemical etching.