A semiconductor device includes a semiconductor element, a first wiring member, a second wiring member, and a terminal. The semiconductor element includes a first main electrode and a second main electrode on a side opposite from the first main electrode. The first wiring member is connected to the first main electrode. The terminal has a first terminal surface connected to the second main electrode and a second terminal surface. The second terminal has four sides. Two of the four sides are parallel to a first direction intersecting the thickness direction, and other two sides of the four sides are parallel to a second direction perpendicular to the thickness direction and the first direction. The second wiring member is connected to the second terminal surface of the terminal through solder, and has a groove. The groove overlaps one or two of the four sides of the second terminal surface.

A power conversion device includes a plurality of semiconductor modules, a plurality of coolers, and a frame. The frame pressurizes and holds a stacked body in which the semiconductor modules and the coolers are alternately stacked. The frame includes a first frame and a second frame that sandwich the stacked body therebetween. The first frame is a plate material bent to surround the stacked body from three directions, and includes a pair of side walls extending in the stacking direction of the stacked body, and an abutting wall extending between the side walls and abutting the stacked body. The abutting wall is bent outward from the frame. Each of the side walls is bent inward from the frame.

A semiconductor package includes a circuit board structure, a first redistribution layer structure and first bonding elements. The circuit board structure includes outermost first conductive patterns and a first mask layer adjacent to the outermost first conductive patterns. The first redistribution layer structure is disposed over the circuit board structure. The first bonding elements are disposed between and electrically connected to the first redistribution layer structure and the outermost first conductive patterns of the circuit board structure. In some embodiments, at least one of the first bonding elements covers a top and a sidewall of the corresponding outermost first conductive pattern.

Implementations of a semiconductor package may include one or more power semiconductor die included in a die module; a first heat sink directly coupled to one or more source pads of the die module; a second heat sink directly coupled to one or more drain pads of the die module; a gate contact coupled with one or more gate pads of the die module; and a coating coupled directly to the die module. The gate contact may be configured to extend through an immersion cooling enclosure.

Memory on Package (MOP) apparatus with reverse CAMM (Compression Attached Memory Module) and compression mount technology (CMT) connector(s). The MOP includes a first (MOP) substrate to which one or more CPUs, SoC, and XPUs that is operatively coupled to one or more CAMMs with a CMT connector(s) disposed between an array of CMT contact pads on the CAMM substrate and an array of CMT contact pad on the substrate. The one or more CAMMs are include multiple memory chips or packages such as LP DDR chips or DDR (S)DRAM chips/packages mounted to an underside of the CAMM substrate via signal coupling means such as a ball grid array (BGA), where the CAMM orientation is inverted such that the memory chips/packages are disposed downward, resulting in a reduced Z-height of the MOP. A MOP may include two CAMMs with a respective CMT connector disposed between the CAMM substrates and the MOP substrate.

A semiconductor device assembly and associated methods are disclosed herein. The semiconductor device assembly includes (1) a substrate having a first side and a second side opposite the first side; (2) a first set of stacked semiconductor devices at the first side of the substrate; (3) a second set of stacked semiconductor devices adjacent to one side of the first set of stacked semiconductor devices; (4) a third set of stacked semiconductor devices adjacent to an opposite side of the first set of stacked semiconductor devices; and (5) a temperature adjusting component at the second side and aligned with the second set of stacked semiconductor devices. The temperature adjusting component is positioned to absorb the thermal energy and thereby thermally isolate the second set of stacked semiconductor devices from the first set of stacked semiconductor devices.

The present disclosure discloses a heat dissipation plate for chip heat dissipation, a server heat dissipation system, and a heating device. One end of the heat dissipation plate may be blocked. Another end of the heat dissipation plate may be provided with a water inlet and a water outlet. A pipeline assembly in the heat dissipation plate may include a plurality of branch water inlet pipelines and a plurality of branch outlet pipelines. One end of the plurality of branch water inlet pipelines may operably connect to the water inlet. One end of the plurality of branch water outlet pipelines may operably connect to the water outlet. Another end of the plurality of branch water inlet pipelines may be operably connected to another end of the plurality of branch water outlet pipelines through a connection pipeline.

Stacked structures having interposers adhered to packaging substrates are disclosed. In one example, a stacked structure can include a laminate substrate. The stacked structure can also include an interposer mounted on the laminate substrate without solder, for example by an electrically nonconductive adhesive layer. A plurality of conductive vias can be extending through the interposer, and through the nonconductive adhesive layer if present, and connecting to the laminate substrate. The stacked structure can also include a redistribution layer (RDL) adjacent to the interposer. The RDL can be configured to electrically connect to an electronic device. Methods for forming such stacked structures are also disclosed.

An apparatus including first and second substrates. The first and second substrates each include a base and at least one peripheral wall extending from the base. One of the at least one peripheral walls of the first or second substrates includes at least one well, and the other of the at least one peripheral walls of the first or the seconds substrate that does not include a well is mechanically anchored to the well. The apparatus includes a stack having a first and second end, and the stack is disposed on the base of the first and/or the second substrates at the first and/or second ends. The stack includes at least one element configured to generate energy.

A semiconductor device includes a die, an encapsulant over a front-side surface of the die, a redistribution structure on the encapsulant, a thermal module coupled to the back-side surface of the die, and a bolt extending through the redistribution structure and the thermal module. The die includes a chamfered corner. The bolt is adjacent to the chamfered corner.