A device includes a first conductive feature in an insulating layer; a dielectric layer over the first conductive feature; a second conductive feature in the dielectric layer, wherein the second conductive feature is over and physically contacting the first conductive feature; an air spacer encircling the second conductive feature, wherein sidewalls of the second conductive feature are exposed to the air spacer; a metal cap covering the second conductive feature and extending over the air spacer, wherein the air spacer is sealed by a bottom surface of the metal cap; a first etch stop layer on the dielectric layer, wherein a sidewall of the first etch stop layer physically contacts a sidewall of the metal cap; and a second etch stop layer extending on a top surface of the metal cap and a top surface of the first etch stop layer.

A semiconductor device is provided with one or more gate fingers (20) that are provided in an active region on a semiconductor substrate (1), and a source finger (30) and a drain finger (40) that are provided in the active region and arranged alternately to allow each gate finger to be sandwiched between the source and drain fingers. The semiconductor device includes terminal circuit (60) that has inductive impedance at the frequency of a signal input to an input terminal of the one or more gate fingers, and is directly or indirectly connected to the one or more gate fingers at an area being spaced away from a connecting position of the input terminal (21a) of the one or more gate fingers (20).

RF devices, and more particularly RF devices with photo-imageable polymers for high frequency enhancements and related methods are disclosed. High frequency enhancements are realized by providing air cavities registered with one or more operating portions of RF devices. The air cavities are formed by photo-imageable polymer structures that provide separation from high dielectric constant materials associated with sealing materials, such as overmold materials, that are typically used for environmental and/or mechanical protection in RF devices. Related methods are disclosed that include forming the photo-imageable polymer structures and corresponding air cavities through various lamination and patterning of photo-imageable polymer layers. Further radiation hardening steps are disclosed that may be applied to the photo-imageable polymer structures after air cavities are formed to promote improved structural integrity of the air cavities during subsequent fabrication steps and during operation of the RF devices.

A high-frequency amplifier includes: a common-source transistor that has gate fingers, drain fingers, and source fingers, amplifies a signal applied to each of the gate fingers as a signal to be amplified, and outputs an amplified signal from each of the drain fingers; a common-gate transistor that has source fingers connected to the drain fingers of the common-source transistor, drain fingers, and gate fingers, and amplifies the amplified signal output from each of the drain fingers of the common-source transistor; a gate bus bar connected to the gate fingers of the common-gate transistor; and capacitors each having a first end connected to the gate bus bar and a second end grounded: wherein the capacitors are arranged at respective positions where impedances obtained by looking toward the respective capacitors from the respective gate fingers of the common-gate transistor are equal to each other.

A transistor includes a plurality of gate fingers that extend in a first direction and are spaced apart from each other in a second direction, each of the gate fingers comprising at least spaced-apart and generally collinear first and second gate finger segments that are electrically connected to each other. The first gate finger segments are separated from the second gate finger segments in the first direction by a gap region that extends in the second direction. A resistor is disposed in the gap region.

A distributed inductance integrated field effect transistor (FET) structure, comprising a plurality of FETs. Each FET comprises a plurality of source regions, a gate region having a plurality of gate fingers extending from a gate bus bar, a drain region having a plurality of drain finger extending from a drain bus bar between the plurality of gate fingers, wherein the gate region controls current flow in a conductive channel between the drain region and source region. A first distributed inductor connects the gate regions of adjacent ones of the plurality of FETs; and a second distributed inductor connects the drain regions of adjacent ones of the plurality of FETs.

An airbridge implements connections on a superconducting chip. It comprises a strip of superconductive material between a first superconductive area and a second superconductive area. A first end of said strip comprises a first planar end portion attached to and parallel with said first superconductive area, and a second end of said strip comprises a respective second planar end portion. A middle portion is located between said first and second planar end portions, forming a bend away from a plane defined by the surfaces of the first and second superconductive areas. First and second separation lines separate the end portions from the middle portion. At least one of said first and second separation lines is directed otherwise than transversally across said strip.

A semiconductor memory device includes; a first impurity region and a second impurity region spaced apart in a semiconductor substrate, a bit line electrically connected to the first impurity region, a storage node contact electrically connected to the second impurity region, an air gap between the bit line and the storage node contact, a landing pad electrically connected to the storage node contact, a buried dielectric pattern on a sidewall of the landing pad and on the air gap, and a spacer capping pattern between the buried dielectric pattern and the air gap.

A transistor includes a plurality of gate fingers that extend in a first direction and are spaced apart from each other in a second direction, each of the gate fingers comprising at least spaced-apart and generally collinear first and second gate finger segments that are electrically connected to each other. The first gate finger segments are separated from the second gate finger segments in the first direction by a gap region that extends in the second direction. A resistor is disposed in the gap region.

An integrated semiconductor device includes an Si substrate, and a high-side transistor and a low-side transistor which configure a half-bridge. A source electrode of a unit transistor configuring the high-side transistor and a drain electrode of a unit transistor configuring the low-side transistor are integrated as a common electrode.