A metal base plate is rectangular in plan view, has a joining region set on a front surface, and has a center line, which is parallel to a pair of short sides that face each other, set in a middle interposed between the pair of short sides. A ceramic circuit board includes a ceramic board that is rectangular in plan view, a circuit pattern that is formed on a front surface of the ceramic board and has a semiconductor chip joined thereto, and a metal plate that is formed on a rear surface of the ceramic board and is joined to the joining region by solder. Here, the solder contains voids and is provided with a stress relieving region at one edge portion that is away from the center line. A density of voids included in the stress relieving region is higher than other regions of the solder.

A power switch module includes a semiconductor die and a conductive busbar. The semiconductor die is electrically conductively mounted to the busbar. The module also includes a dielectric coolant fluid and the busbar and the semiconductor die mounted thereto are immersed in the dielectric coolant fluid.

A circuit module includes a substrate with a patterned metal surface. The patterned metal surface includes a conductive terminal pad, a first conductive pad, and a second conductive pad that is non-adjacent to the conductive terminal pad. A first circuit portion is assembled on the first conductive pad and a second circuit portion is assembled on the second conductive pad. A conductive bridge electrically couples the conductive terminal pad and the second conductive pad. The conductive bridge includes an elevated span extending above and across the first conductive pad.

The semiconductor device includes: a heat spreader; a semiconductor element joined to the heat spreader via a first joining member; a first lead frame joined to the heat spreader via a second joining member; a second lead frame joined to the semiconductor element via a third joining member; and a mold resin. In a cross-sectional shape obtained by cutting at a plane perpendicular to a one-side surface of the heat spreader, an angle on the third joining member side out of two angles formed by a one-side surface of the semiconductor element and a straight line connecting an end point of a joining surface between the third joining member and the semiconductor element and an end point of a joining surface between the third joining member and the second lead frame, is not smaller than 90° and not larger than 135°.

A semiconductor device includes: a semiconductor substrate; an upper surface electrode formed on an upper surface side of the semiconductor substrate; an insulating film formed on the upper surface side of the semiconductor substrate; and a lower surface electrode formed on a lower surface side of the semiconductor substrate and having a larger area than that of the upper surface electrode, wherein the upper surface electrode and the lower surface electrode are electrodes having a compressive stress.

According to one embodiment, a semiconductor device includes at least a package substrate, an external electrode, a mounting substrate, and a mounting electrode. A signal connection point of the external electrode is provided at an end portion in a longitudinal direction of the external electrode. A signal connection point of the mounting electrode is provided at an end portion of the mounting electrode. The end portion of the mounting electrode is opposite to the signal connection point of the external electrode facing to the mounting electrode in the longitudinal direction.

An interconnect structure includes a substrate, a dielectric layer on the substrate, a metal interconnect layer in the dielectric layer and in contact with the substrate, the metal interconnect layer having an upper surface flush with an upper surface of the dielectric layer, and a graphene layer on the metal interconnect layer. The graphene layer insulates a metal from air and prevents the metal from being oxidized by oxygen in the air, thereby increasing the queue time for the CMP process and the device reliability.

A semiconductor package that includes a conductive can, a power semiconductor device electrically and mechanically attached to the inside surface of the can, and an IC semiconductor device copackaged with the power semiconductor device inside the can.

A semiconductor package that includes a conductive can, a power semiconductor device electrically and mechanically attached to the inside surface of the can, and an IC semiconductor device copackaged with the power semiconductor device inside the can.

A dual-side cooling (DSC) semiconductor package includes a first metal-insulator-metal (MIM) substrate having a first insulator layer, first metallic layer, and second metallic layer. A second MIM substrate includes a second insulator layer, third metallic layer, and fourth metallic layer. The third metallic layer includes a first portion having a first contact area and a second portion, electrically isolated from the first portion, having a second contact area. A semiconductor die is coupled with the second metallic layer and is directly coupled with the third metallic layer through one or more solders, sintered layers, electrically conductive tapes, solderable top metal (STM) layers, and/or under bump metal (UBM) layers. The first contact area is electrically coupled with a first electrical contact of the die and the second contact area is electrically coupled with a second electrical contact of the die. The first and fourth metallic layers are exposed through an encapsulant.