According to one embodiment, a semiconductor device includes at least a package substrate, an external electrode, a mounting substrate, and a mounting electrode. A signal connection point of the external electrode is provided at an end portion in a longitudinal direction of the external electrode. A signal connection point of the mounting electrode is provided at an end portion of the mounting electrode. The end portion of the mounting electrode is opposite to the signal connection point of the external electrode facing to the mounting electrode in the longitudinal direction.

A dual-side cooling (DSC) semiconductor package includes a first metal-insulator-metal (MIM) substrate having a first insulator layer, first metallic layer, and second metallic layer. A second MIM substrate includes a second insulator layer, third metallic layer, and fourth metallic layer. The third metallic layer includes a first portion having a first contact area and a second portion, electrically isolated from the first portion, having a second contact area. A semiconductor die is coupled with the second metallic layer and is directly coupled with the third metallic layer through one or more solders, sintered layers, electrically conductive tapes, solderable top metal (STM) layers, and/or under bump metal (UBM) layers. The first contact area is electrically coupled with a first electrical contact of the die and the second contact area is electrically coupled with a second electrical contact of the die. The first and fourth metallic layers are exposed through an encapsulant.

A composite assembly of three stacked joining partners, and a corresponding method. The three stacked joining partners are materially bonded to one another by an upper solder layer and a lower solder layer. An upper joining partner and a lower joining partner are fixed in their height and have a specified distance from one another. The upper solder layer is fashioned from a first solder agent, having a first melt temperature, between the upper joining partner and a middle joining partner. The second solder layer is fashioned from a second solder agent, having a higher, second melt temperature, between the middle joining partner and the lower joining partner. The upper joining partner has an upwardly open solder compensating opening filled with the first solder agent, from which, to fill the gap between the upper joining partner and the middle joining partner, the first solder agent subsequently flows into the gap.

A method of manufacturing a module is disclosed. In one example, the method comprises providing at least one solder body with a base portion and an elevated edge extending along at least part of a circumference of the base portion. At least one carrier, on which at least one electronic component is mounted, is placed in the at least one solder body so that the at least one carrier is positioned on the base portion and is spatially confined by the elevated edge.

The present disclosure relates to a component structure, a power module and a power module assembly structure having the component structure. The component structure comprises: a first bus bar, having one end extending to a first plane to form a first connecting terminal; a second bus bar, comprising a front portion of the second bus bar and a rear portion of the second bus bar, wherein the front portion of the second bus bar is laminated in parallel with the first bus bar, and the rear portion of the second bus bar is extended to a second plane to form a second connecting terminal; and an external circuit comprising a third bus bar, wherein the third bus bar is settled in parallel with the rear portion of the second bus bar, to reduce a parasitic inductance between the first connecting terminal and the second connecting terminal.

Provided is a small-sized inexpensive semiconductor module in which increase of ON resistance and increase of turn-off surge voltage at low temperature are suppressed. The semiconductor module includes: a semiconductor switching element; and a stress application portion provided on one or each of a first surface and a second surface on an opposite side to the first surface of the semiconductor switching element, having a linear expansion coefficient larger than that of a main material of the semiconductor switching element, and having a larger thickness than the semiconductor switching element. The stress application portion generates compressive or tensile stress in the semiconductor switching element through thermal shrinkage or expansion of the stress application portion due to change in temperature. A threshold voltage at which the semiconductor switching element is turned on, decreases in association with increase of a magnitude of the compressive or tensile stress in the semiconductor switching element.

A method of manufacturing a module is disclosed. In one example, the method comprises providing at least one solder body with a base portion and an elevated edge extending along at least part of a circumference of the base portion. At least one carrier, on which at least one electronic component is mounted, is placed in the at least one solder body so that the at least one carrier is positioned on the base portion and is spatially confined by the elevated edge.

Described are microelectronic devices including a substrate formed with multiple build-up layers, and having at least one build-up layer formed of a fiber-containing material. A substrate can include a buildup layers surrounding an embedded die, or outward of the build-up layer surrounding the embedded die that includes a fiber-containing dielectric. Multiple build-up layers located inward from a layer formed of a fiber-containing dielectric will be formed of a fiber-free dielectric.

A header for a semiconductor package, includes an eyelet having a first surface, a second surface opposite to the first surface, a side surface, and a through hole penetrating the eyelet from the first surface to the second surface, a lead inserted through the through hole, and a metal base bonded to the second surface of the eyelet. The lead is bent at the second surface of the eyelet and protrudes from the side surface of the eyelet in a plan view. The metal base is spaced apart from the lead. The lead, located at a position overlapping the eyelet in the plan view, is disposed within a thickness range of the metal base in a side view.

A dual-side cooling (DSC) semiconductor package includes a first metal-insulator-metal (MIM) substrate having a first insulator layer, first metallic layer, and second metallic layer. A second MIM substrate includes a second insulator layer, third metallic layer, and fourth metallic layer. The third metallic layer includes a first portion having a first contact area and a second portion, electrically isolated from the first portion, having a second contact area. A semiconductor die is coupled with the second metallic layer and is directly coupled with the third metallic layer through one or more solders, sintered layers, electrically conductive tapes, solderable top metal (STM) layers, and/or under bump metal (UBM) layers. The first contact area is electrically coupled with a first electrical contact of the die and the second contact area is electrically coupled with a second electrical contact of the die. The first and fourth metallic layers are exposed through an encapsulant.