Patent classifications
H01L23/49894
INTEGRATED CIRCUIT PACKAGE WITH WARPAGE CONTROL USING CAVITY FORMED IN LAMINATED SUBSTRATE BELOW THE INTEGRATED CIRCUIT DIE
A support substrate includes an insulating core layer, an electrically conductive layer over the insulating core layer and a solder mask layer over the electrically conductive layer. A back side of an integrated circuit chip is mounted to an upper surface of the support substrate at a die attach location. The upper surface of the support substrate includes a cavity located within the die attach location, where the cavity extends under the back side of the integrated circuit chip. The cavity is defined by an area where the solder mask layer and at least a portion of the electrically conductive layer have been removed. Bonding wires connect connection pads on a front side of the integrated circuit chip to connection pad on the upper surface of the support substrate.
PHOTOSENSITIVE RESIN COMPOSITION, PHOTOSENSITIVE RESIN FILM, MULTILAYERED PRINTED WIRING BOARD, SEMICONDUCTOR PACKAGE, AND METHOD FOR PRODUCING MULTILAYERED PRINTED WIRING BOARD
Provided is a photosensitive resin composition containing: a photopolymerizable compound (A) having an ethylenically unsaturated group; a photopolymerization initiator (B); and an inorganic filler (F), in which the photopolymerizable compound (A) having an ethylenically unsaturated group includes a photopolymerizable compound (A1) having an acidic substituent and an alicyclic structure together with an ethylenically unsaturated group, and the inorganic filler (F) includes an inorganic filler surface-treated with a coupling agent without at least one functional group selected from the group consisting of an amino group and a (meth)acryloyl group. The present disclosure also provides a photosensitive resin composition for photo via formation, and a photosensitive resin composition for interlayer insulating layer. The present disclosure further provides: a photosensitive resin film and a photosensitive resin film for interlayer insulating layer, each of which contains the photosensitive resin composition; a multilayered printed wiring board and a semiconductor package; and a method for producing a multilayered printed wiring board.
Electronic IC device comprising integrated optical and electronic circuit component and fabrication method
A first circuit structure of an electronic IC device includes comprises light-sensitive optical circuit components. A second circuit structure of the electronic IC device includes an electronic circuit component and an electrically-conductive layer extending between and at a distance from the optical circuit components and the electronic circuit component. Electrical connections link the optical circuit components and the electronic circuit component. These electrical connections are formed in holes which pass through dielectric layers and the intermediate conductive layer. Electrical insulation rings between the electrical connections and the conductive layer are provided which surround the electrical connections and have a thickness equal to a thickness of the conductive layer.
Semiconductor package
A semiconductor package includes a base substrate; an interposer substrate including a semiconductor substrate having a first surface facing the base substrate and a second surface, opposing the first surface, and a passivation layer on at least a portion of the first surface; a plurality of connection bumps between the base substrate and the interposer substrate; an underfill resin in a space between the base substrate and the interposer substrate; and a first semiconductor chip and a second semiconductor chip on the interposer substrate. The interposer substrate has a first region, in which the plurality of connection bumps are included, and a second region and a third region adjacent a periphery of the first region, and the passivation layer is in the second region and includes a first embossed pattern in the second region.
SEMICONDUCTOR DEVICE AND POWER CONVERTER
A semiconductor device includes a semiconductor element, a first wiring member, a second wiring member, and a terminal. The semiconductor element includes a first main electrode and a second main electrode on a side opposite from the first main electrode. The first wiring member is connected to the first main electrode. The terminal has a first terminal surface connected to the second main electrode and a second terminal surface. The second terminal has four sides. Two of the four sides are parallel to a first direction intersecting the thickness direction, and other two sides of the four sides are parallel to a second direction perpendicular to the thickness direction and the first direction. The second wiring member is connected to the second terminal surface of the terminal through solder, and has a groove. The groove overlaps one or two of the four sides of the second terminal surface.
PRINTED CIRCUIT BOARD AND SEMICONDUCTOR PACKAGE WHICH INCLUDE MULTI-LAYERED PHOTOSENSITIVE INSULATING LAYER, AND METHOD OF MANUFACTURING THE SAME
A printed circuit board may include a substrate body portion, conductive patterns on a top surface of the substrate body portion, and a photosensitive insulating layer on the top surface of the substrate body portion and including an opening exposing at least one of the conductive patterns. The photosensitive insulating layer includes first to third sub-layers stacked sequentially. The first sub-layer includes an amine compound or an amide compound A refractive index of the second sub-layer is lower than a refractive index of the third sub-layer. A photosensitizer content of the second sub-layer is higher than a photosensitizer content of the third sub-layer.
CHIP-ON-FILM PACKAGE
A chip-on-film package may include a film substrate including a chip region and an edge region, a semiconductor chip provided on the chip region and mounted on a top surface of the film substrate, the semiconductor chip including a chip pad adjacent to a bottom surface thereof, an input line and an output line provided on the edge region and disposed on the top surface of the film substrate, a connection terminal interposed between the film substrate and the semiconductor chip, and a redistribution pattern disposed between the semiconductor chip and the connection terminal.
Methods and devices related to reduced packaging substrate deformation
A packaging substrate can include a first surface and a second opposing surface, the first surface having a mounting region configured to receive electronic components, and electrical contacts formed on the second opposing surface. A saw street region can surround the mounting region and the electrical contacts, a metal layer and a solder mask layer being formed within the saw street region on the second opposing surface, and the solder mask layer being formed over the metal layer. An electronic module can include a packaging substrate including a first surface and a second opposing surface, the first surface including a mounting region. A plurality of electronic components can be mounted on the mounting region. A ground pad can be formed on the second opposing surface of the packaging substrate, the ground pad including a solder mask layer formed thereon, the solder mask layer having a plurality of openings.
Semiconductor package substrate and method of manufacturing semiconductor package using the same
Provided in a semiconductor package substrate including a semiconductor chip including a connection pad, an encapsulant encapsulating at least a portion of the semiconductor chip, a connection member disposed on the semiconductor chip and the encapsulant, the connection member including a redistribution layer that is electrically connected to the connection pad, a first passivation layer disposed on the connection member, and an adhesive layer disposed on at least one of a top surface of the encapsulant and a bottom surface of the first passivation layer in a region outside of the semiconductor chip.
Transient Electronic Device With Ion-Exchanged Glass Treated Interposer
A transient electronic device utilizes a glass-based interposer that is treated using ion-exchange processing to increase its fragility, and includes a trigger device operably mounted on a surface thereof. An integrated circuit (IC) die is then bonded to the interposer, and the interposer is mounted to a package structure where it serves, under normal operating conditions, to operably connect the IC die to the package I/O pins/balls. During a transient event (e.g., when unauthorized tampering is detected), a trigger signal is transmitted to the trigger device, causing the trigger device to generate an initial fracture force that is applied onto the glass-based interposer substrate. The interposer is configured such that the initial fracture force propagates through the glass-based interposer substrate with sufficient energy to both entirely powderize the interposer, and to transfer to the IC die, whereby the IC die also powderizes (i.e., visually disappears).