A transistor includes a gate electrode, a ferroelectric layer, a channel layer, a gas impermeable layer, a dielectric layer, a source line and a bit line. The ferroelectric layer is disposed on the gate electrode. The channel layer is disposed on the ferroelectric layer. The gas impermeable layer is disposed in between the channel layer and the gate electrode, and in contact with the ferroelectric layer. The dielectric layer is surrounding the ferroelectric layer and the channel layer, and in contact with the gas impermeable layer. The source line and the bit line are embedded in the dielectric layer and connected to the channel layer.

The present disclosure describes a structure that includes a substrate with first and second sides, a device layer disposed on the first side of the substrate, having a fault detection area on a back-side surface of the device layer configured to emit a signal that is indicative of a presence or an absence of a defect in the device layer, a first interconnect structure disposed on a front-side of the device layer, and a second interconnect structure disposed on the second side of the substrate, having a metal-free region aligned with the fault detection area and a first metal layer having first and second conductive lines disposed substantially parallel to each other. First and second sidewalls of the first and second conductive lines, respectively, facing each other are substantially aligned with first and second sides of the fault detection area.

The present disclosure describes a structure that includes a substrate with first and second sides, a device layer disposed on the first side of the substrate, having a fault detection area on a back-side surface of the device layer configured to emit a signal that is indicative of a presence or an absence of a defect in the device layer, a first interconnect structure disposed on a front-side of the device layer, and a second interconnect structure disposed on the second side of the substrate, having a metal-free region aligned with the fault detection area and a first metal layer having first and second conductive lines disposed substantially parallel to each other. First and second sidewalls of the first and second conductive lines, respectively, facing each other are substantially aligned with first and second sides of the fault detection area.

A method includes forming a trench in a semiconductor layer of a device wafer and depositing a liner on the trench sidewalls. The liner is removed from the trench bottom, and the trench is deepened anisotropically to form an extension fully along the trench, or locally by applying a mask. The semiconductor material is removed outwardly from the extension by etching to create a cavity wider than the trench and below the liner. A space formed by the trench and cavity is filled with electrically conductive material to form a buried interconnect rail comprising a narrow portion in the trench and a wider portion in the cavity. The wider portion can be contacted by a TSV connection, enabling a contact area between the connection and buried rail. The etching forms a wider rail portion at a location remote from active devices formed on the front surface of the semiconductor layer.

The present invention provides a metal interconnection structure and a manufacturing method thereof, the metal interconnection structure includes: metal interconnection lines disposed at intervals, first metal layers respectively disposed on the metal interconnection lines; second metal layers respectively disposed on the first metal layers; dielectric layers disposed on both sides of the first metal layer and the second metal layer and having a gap with both the first metal layer and the second metal layer; and a metal diffusion covering layer covering the dielectric layer and the second metal layer. In the present invention, by disposing the dielectric layer on both sides of the first metal layer and the second metal layer, and the dielectric layer has a gap with both the first metal layer and the second metal layer, and the formed metal interconnection structure reduces parasitic capacitance due to the gap, and the gaps existing between the first metal layer and the dielectric layer and between the second metal layer and the dielectric layer can further reduce the diffusion of metal ions to the dielectric layer.

The present invention provides a metal interconnection structure and a manufacturing method thereof, the metal interconnection structure includes: metal interconnection lines disposed at intervals, first metal layers respectively disposed on the metal interconnection lines; second metal layers respectively disposed on the first metal layers; dielectric layers disposed on both sides of the first metal layer and the second metal layer and having a gap with both the first metal layer and the second metal layer; and a metal diffusion covering layer covering the dielectric layer and the second metal layer. In the present invention, by disposing the dielectric layer on both sides of the first metal layer and the second metal layer, and the dielectric layer has a gap with both the first metal layer and the second metal layer, and the formed metal interconnection structure reduces parasitic capacitance due to the gap, and the gaps existing between the first metal layer and the dielectric layer and between the second metal layer and the dielectric layer can further reduce the diffusion of metal ions to the dielectric layer.

An integrated circuit includes a set of transistors including a set of active regions, a set of power rails, a first set of conductors and a first conductor. The set of active regions extends in a first direction, and is on a first level. The set of power rails extends in the first direction and is on a second level. The set of power rails has a first width. The first set of conductors extends in the first direction, is on the second level, and overlaps the set of active regions. The first set of conductors has a second width. The first conductor extends in the first direction, is on the second level and is between the first set of conductors. The first conductor has the first width, electrically couples a first transistor of the set of transistors to a second transistor of the set of transistors.

A method includes forming a first conductive feature in a first dielectric layer, forming a first metal cap over and contacting the first conductive feature, forming an etch stop layer over the first dielectric layer and the first metal cap, forming a second dielectric layer over the etch stop layer; and etching the second dielectric layer and the etch stop layer to form an opening. The first conductive feature is exposed to the opening. The method further includes selectively depositing a second metal cap at a bottom of the opening, forming an inhibitor film at the bottom of the opening and on the second metal cap, selectively depositing a conductive barrier in the opening, removing the inhibitor film, and filling remaining portions of the opening with a conductive material to form a second conductive feature.

An integrated circuit includes a plurality of standard cells including first and second standard cells arranged adjacent to each other in a first direction, and first, second, and third metal layers sequentially stacked in a vertical direction. At least one power segment is arranged adjacent a region where at least one of the first standard cell and the second standard cell is arranged. The at least one power segment is configured to provide power to the plurality of standard cells and is formed as a pattern of the third metal layer extending in a second direction.

A semiconductor device includes a first metal interconnection disposed on a substrate, a second metal interconnection disposed on the first metal interconnection, a first contact via disposed between the first metal interconnection and the second metal interconnection, a first serpent metal line connecting to a first end of the first metal interconnection, and a second serpent metal line connecting to a second end of the first metal interconnection. Preferably, the first serpent metal line, the second serpent metal line, and the first metal interconnection are on a same level.