A method of fabricating a bridged multi-chip assembly structure includes providing a carrier substrate. The method further includes arranging a plurality of chips on the carrier substrate in a predetermined layout. Each chip has a front surface including a set of terminals formed thereon. The method further includes depositing a molding material between the plurality of chips and on the carrier substrate. The method further includes removing the carrier substrate from the plurality of chips fixed by the molding material. The method further includes bonding a bridge chip to corresponding sets of terminals of at least two chips of the plurality of chips fixed by the molding material.

A semiconductor package includes a logic die surrounded by a molding compound; a memory die disposed in proximity to the logic die; a plurality of vias around the logic die for electrically connecting the logic die to the memory die. Each of the plurality of vias has an oval shape or a rectangular shape when viewed from above. The vias have a horizontal pitch along a first direction and a vertical pitch along a second direction. The vertical pitch is greater than the horizontal pitch.

A package structure includes first/second/third package components, a thermal interface material (TIM) structure overlying the first package component opposite to the second package component, and a heat dissipating component disposed on the third package component and thermally coupled to the first package component through the TIM structure. The first package component includes semiconductor dies and an insulating encapsulation encapsulating the semiconductor dies, the second package component is interposed between the first and third package components, and the semiconductor dies are electrically coupled to the third package component via the second package component. The TIM structure includes a dielectric dam and thermally conductive members including a conductive material, disposed within areas confined by the dielectric dam, and overlying the semiconductor dies. A manufacturing method of a package structure is also provided.

A semiconductor structure and a manufacturing method thereof are provided. The method includes the following steps. A plurality of conductive balls is placed over a circuit substrate, where each of the conductive balls is placed over a contact area of one of a plurality of contact pads that is accessibly revealed by a patterned mask layer. The conductive balls are reflowed to form a plurality of external terminals with varying heights connected to the contact pads of the circuit substrate, where a first external terminal of the external terminals formed in a first region of the circuit substrate and a second external terminal of the external terminals formed in a second region of the circuit substrate are non-coplanar.

A semiconductor assembly package is provided. The semiconductor package assembly includes a system-on-chip (SOC) package, a memory package and a heat spreader. The SOC package includes a logic die and a first substrate. The logic die has pads on it. The first substrate is electrically connected to the logic die by the pads. The memory package includes a second substrate and a memory die. The second substrate has a top surface and a bottom surface. The memory die is mounted on the top surface of the second substrate and is electrically connected to the second substrate using bonding wires. The heat spreader is disposed between the SOC package and the memory package, wherein the heat spreader is in contact with a back surface of the logic die away from the pads.

Provided is a package-on-package (PoP). The PoP includes a lower package, an upper package on the lower package, an interposer substrate disposed between the lower package and the upper package, and a plurality of balls connecting the interposer substrate to the upper package, in which the lower package includes a first substrate, and a first die and a second die disposed side by side in a horizontal direction, on the first substrate, in which the upper package includes a second substrate, a third die on the second substrate, and a plurality of ball pads disposed on a surface of the second substrate, the interposer substrate comprises on a surface thereof a plurality of ball lands to which a plurality of balls are attached, and at least some of the plurality of ball lands overlap the first die and the second die in a vertical direction that intersects the horizontal direction.

A package structure is provided. The package structure includes a semiconductor die and a thermoelectric structure disposed on the semiconductor die. The thermoelectric structure includes P-type semiconductor blocks, N-type semiconductor blocks and metal pads. The P-type semiconductor blocks and the N-type semiconductor blocks are arranged in alternation with the metal pads connecting the P-type semiconductor blocks and the N-type semiconductor blocks. When a current flowing through one of the N-type semiconductor block, one of the metal pad, and one of the P-type semiconductor block in order, the metal pad between the N-type semiconductor block and the P-type semiconductor block forms a cold junction which absorbs heat generated by the semiconductor die.

Composite dielectric structures for semiconductor die assemblies, and associated systems and methods are disclosed. In some embodiments, the composite dielectric structure includes a flexible dielectric layer configured to conform to irregularities (e.g., particles, defects) at a bonding interface of directly bonded semiconductor dies (or wafers). The flexible dielectric layer may include a polymer material configured to deform in response to localized pressure generated by the irregularities during bonding process steps. The composite dielectric structure includes additional dielectric layers sandwiching the flexible dielectric layer such that the composite dielectric structure can provide robust bonding strength to other dielectric layers through the additional dielectric layers. In some embodiments, a chemical vapor deposition process may be used to form the composite dielectric structure utilizing siloxane derivatives as a precursor.

The invention discloses a semiconductor package structure including a package carrier, at least one electronic component, a packaging layer, a support component and a shielding layer. The electronic component is disposed on a first surface of the package carrier. The packaging layer is disposed on the first surface and covers the electronic component. The support component is embedded in the packaging layer to surround the electronic component. An end surface of the support component is electrically connected to a build-up circuit and electrically grounded. A patterned metal layer of the shielding layer is electrically connected to the support component. The shielding range of the patterned metal layer covers at least electronic component. A shielding space, which covers the electronic component, is formed by the support component and the shielding layer. In addition, a semiconductor EMI shielding component and a method of making a semiconductor package structure are also disclosed.

A semiconductor package includes a package substrate, a semiconductor stack on the package substrate, a passive device on the package substrate and spaced apart from the semiconductor stack, and a stiffener on the package substrate and extending around an outer side of the semiconductor stack. The stiffener includes a first step surface extends over the passive device. A width of a bottom surface of the stiffener is smaller than a width of a top surface of the stiffener.