A method of forming a power rail to semiconductor devices comprising removing a portion of the gate structure forming a gate cut trench separating a first active region of fin structures from a second active region of fin structures. A conformal etch stop layer is formed in the gate cut trench. A fill material is formed on the conformal etch stop layer filling at least a portion of the gate cut trench. The fill material has a composition that is etched selectively to the conformal etch stop layer. A power rail is formed in the gate cut trench. The conformal etch stop layer obstructs lateral etching during forming the power rail to substantially eliminate power rail to gate structure shorting.

A method of forming a power rail to semiconductor devices comprising removing a portion of the gate structure forming a gate cut trench separating a first active region of fin structures from a second active region of fin structures. A conformal etch stop layer is formed in the gate cut trench. A fill material is formed on the conformal etch stop layer filling at least a portion of the gate cut trench. The fill material has a composition that is etched selectively to the conformal etch stop layer. A power rail is formed in the gate cut trench. The conformal etch stop layer obstructs lateral etching during forming the power rail to substantially eliminate power rail to gate structure shorting.

Provided is a semiconductor device, including: a first electrode layer including a first wiring member and a second electrode layer including a second wiring member, the first electrode layer and the second electrode layer being disposed to face each other; a semiconductor element disposed in a gap between the first and second electrode layers, and electrically connected to the first and second electrode layers; and a via disposed in the gap between the first and second electrode layers, electrically connected to the first and second electrode layers, and configured to detect a state of the semiconductor element by being fractured at a predetermined temperature and losing electric connection.

A power semiconductor module includes an electrically insulating carrier plate with a structured, electrically conducting metallization layer disposed on a surface thereof, and a connection pin having two ends and being adhered to the carrier plate, one end of the connection pin being electrically connected to the metallization layer. The module further includes a semiconductor device adhered to the carrier plate and electrically connected to the metallization layer, and a discrete circuit including a voltage-or-current-or-both controlling device, the voltage-or-current-or-both controlling device being operatively coupled with the semiconductor device and being integrated in the connection pin at one of or between the two ends of the connection pin.

A semiconductor device with an identification structure is provided. The semiconductor device includes a substrate and a metallization structure over the substrate. The metallization structure includes an interconnection region having a plurality of metal layers and an identification region isolated from the interconnection region. The identification region has an identification structure leveled with one of the metal layer. The identification structure includes at least one exposing recess and at least one exposing fuse. A method for manufacturing a semiconductor device with an identification structure and a method for tracing a production information of a semiconductor device are also provided.

A terminal protection circuit of a semiconductor chip, including a first pad serving as a ground terminal of the semiconductor chip, a ground line extending along an outer periphery of the semiconductor chip and being connected to the first pad, and an overcurrent sensing circuit. The overcurrent sensing circuit has a second pad, a threshold voltage generating circuit, a comparator having inverting and non-inverting input terminals respectively connected to the threshold voltage generating circuit and the second pad, the comparator comparing a current detection signal and a threshold voltage received respectively at the non-inverting and inverting input terminals, a first input protection element connected between the second pad and a first position on the chip-peripheral ground line, and a potential shift element connected between the inverting input terminal of the comparator and the first position, for shifting the threshold voltage thereat according to a potential at the first position.

A terminal protection circuit of a semiconductor chip, including a first pad serving as a ground terminal of the semiconductor chip, a ground line extending along an outer periphery of the semiconductor chip and being connected to the first pad, and an overcurrent sensing circuit. The overcurrent sensing circuit has a second pad, a threshold voltage generating circuit, a comparator having inverting and non-inverting input terminals respectively connected to the threshold voltage generating circuit and the second pad, the comparator comparing a current detection signal and a threshold voltage received respectively at the non-inverting and inverting input terminals, a first input protection element connected between the second pad and a first position on the chip-peripheral ground line, and a potential shift element connected between the inverting input terminal of the comparator and the first position, for shifting the threshold voltage thereat according to a potential at the first position.

A semiconductor device has a resistance element including a metal block, a resin layer disposed on the metal block, and a resistance film disposed on the resin layer and an insulated circuit board including an insulating plate and a circuit pattern disposed on the insulating plate and having a bonding area on a front surface thereof to which a back surface of the metal block of the resistance element is bonded. The area of the circuit pattern is larger in plan view than that of a front surface of the resistance element. The metal block has a thickness greater than that of the circuit pattern in a direction orthogonal to the back surface of the metal block. As a result, the metal block properly conducts heat generated by the resistance film of the resistance element to the circuit pattern.

A method includes providing a first lead frame that includes a first die pad and a first row of leads, providing a connection lug, mounting a first semiconductor die on the first die pad, the first semiconductor die including first and second voltage blocking terminals, electrically connecting the connection lug to one of the first and second voltage blocking terminals, electrically connecting a first one of the leads from the first row to an opposite one of the first and second voltage blocking terminals, and forming an encapsulant body of electrically insulating material that encapsulates first die pad and the first semiconductor die. After forming the encapsulant body, the first row of leads each protrude out of a first outer face of the encapsulant body and the connection lug protrudes out of a second outer face of the encapsulant body.

Semiconductor devices having inductive structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a substrate and at least one circuit component coupled to the substrate. The semiconductor device can further include an inductive structure carried by the substrate and having a stack of alternating first and second layers. In some embodiments, the first layers comprise an oxide material and the second layers each include a coil of conductive material. The coils of conductive material can be electrically coupled (a) together to form an inductor and (b) to the at least one circuit component.