An integrated circuit includes a resistive material layer formed on a substrate, a metal layer formed on the resistive material layer, a bipolar transistor formed on the substrate, and a resistive element formed on the substrate. The bipolar transistor includes, as a sub-layer, the metal layer formed in a first region, and also includes a collector layer formed on the sub-collector layer. The resistive element is constituted by the resistive material layer formed in a second region.

A semiconductor device package comprises a semiconductor switching device having a body, including a first side, and an opposing second side coupled to a substrate. A gate terminal is defined on the semiconductor switching device body first side, the gate terminal having a first side, and an opposing second side facing the semiconductor switching device body. A first gate resistor is disposed on the gate terminal first side, and coupled electrically in series with the gate terminal.

An integrated circuit package is disclosed. The integrated circuit package includes a first integrated circuit die, a second integrated circuit die, an organic substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the organic substrate, a multi-die interconnect bridge (EMIB) embedded within the organic substrate, and a termination resistor associated with a circuit in the first integrated circuit die, wherein the termination resistor is located within the multi-die interconnect bridge embedded within the organic substrate.

In a method of manufacturing a semiconductor device, a fin structure, which includes a stacked layer of first semiconductor layers and second semiconductor layers disposed over a bottom fin structure and a hard mask layer over the stacked layer, is formed. An isolation insulating layer is formed. A sacrificial cladding layer is formed over at least sidewalls of the exposed hard mask layer and stacked layer. A first dielectric layer is formed. A second dielectric layer is formed over the first dielectric layer. The second dielectric layer is recessed. A third dielectric layer is formed on the recessed second dielectric layer. The third dielectric layer is partially removed to form a trench. A fourth dielectric layer is formed by filling the trench with a dielectric material, thereby forming a wall fin structure.

A configurable capacitance device includes a semiconductor substrate including a plurality of integrally formed capacitors; and a separate interconnect structure coupled to the semiconductor substrate, wherein the separate interconnect structure is configurable to electrically couple two or more of the plurality of integrally formed capacitors together in a parallel configuration.

A semiconductor device includes a first terminal, a second terminal positioned away from the first terminal, a first resistive segment coupled between the first terminal and the second terminal, a third terminal positioned away from the first terminal and the second terminal, a second resistive segment coupled between the second terminal and third terminal, a first floating plate disposed physically proximate the first resistive segment and including a first end coupled to one of the first terminal and the second terminal, and a second floating plate disposed physically proximate the second resistive segment and including a first end coupled to one of the second terminal and the third terminal.

Embodiments herein may describe techniques for an integrated circuit including a FinFET transistor to be used as an antifuse element having a path through a fin area to couple a source electrode and a drain electrode after a programming operation is performed. A FinFET transistor may include a source electrode in contact with a source area, a drain electrode in contact with a drain area, a fin area including silicon and between the source area and the drain area, and a gate electrode above the fin area and above the substrate. After a programming operation is performed to apply a programming voltage between the source electrode and the drain electrode to generate a current between the source electrode, the fin area, and the drain electrode, a path may be formed through the fin area to couple the source electrode and the drain electrode. Other embodiments may be described and/or claimed.

A method for fabricating an electrical or electronic device package includes providing a first plateable encapsulation layer; activating first selective areas on a main surface of the first plateable encapsulation layer; forming a first metallization layer by electrolytic or electroless plating on the first activated areas; and fabricating a passive electrical component on the basis of the first metallization layer.

A semiconductor apparatus includes a mounting board, a system on chip (SOC) package and a memory package which are provided on the mounting board. The SOC package includes a semiconductor chip and a package substrate on which the semiconductor chip is mounted. The semiconductor apparatus further includes a signal wiring line through which a signal between the semiconductor chip and the memory package is transmitted, being provided on the package substrate and in the mounting board and a measurement terminal connected to the signal wiring line on main surface of the package substrate.

A microelectronic device includes a doped region of semiconductor material having a first region and an opposite second region. The microelectronic device is configured to provide a first operational potential at the first region and to provide a second operational potential at the second region. The microelectronic device includes field plate segments in trenches extending into the doped region. Each field plate segment is separated from the semiconductor material by a trench liner of dielectric material. The microelectronic device further includes circuitry electrically connected to each of the field plate segments. The circuitry is configured to apply bias potentials to the field plate segments. The bias potentials are monotonic with respect to distances of the field plate segments from the first region of the doped region.