H01L24/81

DISPLAY DEVICE
20230052793 · 2023-02-16 ·

A display device including: a substrate including pixel electrodes; a passivation layer on the substrate, a groove in the passivation layer between the pixel electrodes;

contact electrodes on the pixel electrodes; and a light-emitting element layer comprising a plurality of light-emitting elements respectively bonded onto the contact electrodes and having a plurality of semiconductor layers thereon. The groove does not overlap the plurality of light-emitting elements.

ELECTRONIC DEVICE AND MANUFACTURING METHOD OF ELECTRONIC DEVICE
20230052081 · 2023-02-16 · ·

Disclosed are an electronic device and a manufacturing method of an electronic device. The manufacturing method includes the following. A first substrate is provided. The first substrate includes a plurality of chips. A second substrate is provided. A transfer process is performed to sequentially transfer a first chip and a second chip among the chips to the second substrate. The second chip is adjacent to the first chip. A first angle is between a first extension direction of a first side of the first chip and an extension direction of a first boundary of the second substrate. A second angle is between a second extension direction of a second side of the second chip and the extension direction of the first boundary of the second substrate. The first angle is different from the second angle.

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure and a manufacturing method thereof are provided. The method includes the following steps. A plurality of conductive balls is placed over a circuit substrate, where each of the conductive balls is placed over a contact area of one of a plurality of contact pads that is accessibly revealed by a patterned mask layer. The conductive balls are reflowed to form a plurality of external terminals with varying heights connected to the contact pads of the circuit substrate, where a first external terminal of the external terminals formed in a first region of the circuit substrate and a second external terminal of the external terminals formed in a second region of the circuit substrate are non-coplanar.

DISPLAY DEVICE AND METHOD FOR FABRICATION THEREOF
20230053037 · 2023-02-16 ·

A display device and method for fabrication thereof includes a plurality of pixel electrodes and common electrode connection parts that are spaced from each other on a first substrate, a plurality of light emitting elements on the plurality of pixel electrodes, a plurality of common electrode elements on the common electrode connection parts, and a common electrode layer on the plurality of light emitting elements and the plurality of common electrode elements, wherein each of the plurality of light emitting element includes a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer, each of the plurality of common electrode elements includes at least the second semiconductor layer, and the common electrode layer includes a same material as the second semiconductor layer to be connected to the second semiconductor layers of the plurality of light emitting elements.

VERTICAL CAVITY SURFACE EMITTING LASER ILLUMINATOR PACKAGE WITH EMBEDDED CAPACITOR
20230047740 · 2023-02-16 ·

In some implementations, a vertical cavity surface emitting laser (VCSEL) package may include a substrate. The VCSEL package may include a VCSEL disposed on a surface of the substrate. The VCSEL package may include a VCSEL driver disposed on the surface of the substrate. The VCSEL package may include an embedded capacitor electrically connected to the VCSEL and the VCSEL driver. The embedded capacitor may be formed from a subset of layers of the substrate. The capacitor may be associated with a first capacitance that is different from a second capacitance of at least one other capacitor associated with the substrate.

DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME
20230049315 · 2023-02-16 ·

A display device includes first pixel circuit unit, second pixel circuit unit, third pixel circuit unit, and fourth pixel circuit unit spaced from one another, first pixel electrode on the first pixel circuit unit, second pixel electrode on the second pixel circuit unit, third pixel electrode on the third pixel circuit unit, fourth pixel electrode on the fourth pixel circuit unit, first light-emitting element electrically connected to the first pixel electrode, the first light-emitting element configured to emit first light, second light-emitting element electrically connected to the second pixel electrode, the second light-emitting element configured to emit second light, and third light-emitting element electrically connected to the third pixel electrode, the third light-emitting element configured to emit third light. A length of the first light-emitting element in a first direction is greater than each of a length of the second and third light-emitting elements in the first direction.

DISPLAY DEVICE AND METHOD FOR FABRICATION THEREOF

A display device and method for fabrication thereof are provided. The display device includes a first substrate, pixel electrodes on the first substrate, light emitting elements respectively on the pixel electrodes, and including first semiconductor layers, second semiconductor layers, active layers respectively between the first semiconductor layers and the second semiconductor layers, a first light emitting element including a first active layer of the active layers, a second light emitting element including a second active layer of the active layers that is different from the first active layer, a third light emitting element including a third active layer of the active layers that is different from the first and second active layers, and a fourth light emitting element including a fourth active layer of the active layers that is different from the first to third active layers, and a common electrode layer on the light emitting elements.

Semiconductor package having semiconductor element with pins and formation method thereof

A semiconductor package and a method of forming the semiconductor package are provided. The method includes providing a first substrate, forming a wiring structure containing at least two first wiring layers, disposing a first insulating layer between adjacent two first wiring layers, and patterning the first insulating layer to form a plurality of first through-holes. The adjacent two first wiring layers are electrically connected to each other through the plurality of first through-holes. The method also includes providing at least one semiconductor element each including a plurality of pins. In addition, the method includes disposing the plurality of pins of the each semiconductor element on a side of the wiring structure away from the first substrate. Further, the method includes encapsulating the at least one semiconductor element, and placing a ball on a side of the wiring structure away from the at least one semiconductor element.

Package comprising a die and die side redistribution layers (RDL)

A package that includes a second redistribution portion, a die coupled to the second redistribution portion, an encapsulation layer encapsulating the die, and a first redistribution portion coupled to the second redistribution portion. The first redistribution portion is located laterally to the die. The first redistribution portion is located over the second redistribution portion. The first redistribution portion and the second redistribution portion are configured to provide one or more electrical paths for the die.

Flip chip package and circuit board thereof

A flip chip package includes a circuit board, a chip and a solder layer. The chip is mounted on an inner bonding area of the circuit board. The solder layer is located between the circuit board and the chip for bonding bumps to inner leads and a T-shaped circuit unit is on the inner bonding area. The T-shaped circuit unit has a main part, a connection part, and a branch part. The connection part is connected to the main and branch parts, respectively. The main part extends along a lateral direction and the branch part extends outwardly along a longitudinal direction. The connection part is narrower than the main part in width so as to inhibit solder shorts caused by solder overflow on the branch part.