The technology relates to an integrated circuit (IC) package. The IC package may include a substrate. An IC die may be mounted to the substrate. One or more photonic modules may be attached to the substrate and one or more serializer/deserializer (SerDes) interfaces may connect the IC die to the one or more photonic modules. The IC die may be an application specific integrated circuit (ASIC) die and the one or more photonic modules may include a photonic integrated circuit (PIC) and fiber array. The one or more photonic modules may be mounted to one or more additional substrates which may be attached to the substrate via one or more sockets.

A sensor package structure includes a substrate, a sensor chip disposed on and electrically coupled to the substrate, an opaque support (e.g., a ring-shaped solder mask) disposed on the sensor chip, and a light permeable layer disposed on the opaque support. The sensor chip includes a sensing region. The opaque support surrounds the sensing region, and inner lateral sides of the opaque support form a light-scattering loop wall. The light permeable layer, the light-scattering loop wall of the opaque support, and the sensor chip jointly define an enclosed space therein. When light passes through the light permeable layer and impinges onto the light-scattering loop wall at an incident angle, the light-scattering loop wall scatters the light into multiple rays at angles different from the incident angle.

The technology relates to an integrated circuit (IC) package. The IC package may include a substrate. An IC die may be mounted to the substrate. One or more photonic modules may be attached to the substrate and one or more serializer/deserializer (SerDes) interfaces may connect the IC die to the one or more photonic modules. The IC die may be an application specific integrated circuit (ASIC) die and the one or more photonic modules may include a photonic integrated circuit (PIC) and fiber array. The one or more photonic modules may be mounted to one or more additional substrates which may be attached to the substrate via one or more sockets.

A sensor package structure includes a substrate, a sensor chip disposed on and electrically coupled to the substrate, an opaque support (e.g., a ring-shaped solder mask) disposed on the sensor chip, and a light permeable layer disposed on the opaque support. The sensor chip includes a sensing region. The opaque support surrounds the sensing region, and inner lateral sides of the opaque support form a light-scattering loop wall. The light permeable layer, the light-scattering loop wall of the opaque support, and the sensor chip jointly define an enclosed space therein. When light passes through the light permeable layer and impinges onto the light-scattering loop wall at an incident angle, the light-scattering loop wall scatters the light into multiple rays at angles different from the incident angle.

An exemplary micro-device and substrate structure includes a destination substrate and one or more contact pads disposed thereon, a micro-device disposed on or over the destination substrate, and a layer of cured adhesive disposed on the destination substrate. The micro-device comprises at least one electrical contact. The at least one electrical contact is in direct electrical contact with the one or more contact pads. The adhesive layer adheres the micro-device to the destination substrate and is in contact with the one or more contact pads. An exemplary method of making a micro-device and substrate structure includes providing a destination substrate and one or more contact pads disposed thereon, coating a layer of curable adhesive, disposing a micro-device comprising at least one electrical contact on the layer and curing the layer thereby directly electrically contacting the at least one electrical contact with the one or more contact pads.

The technology relates to an integrated circuit (IC) package. The IC package may include a substrate. An IC die may be mounted to the substrate. One or more photonic modules may be attached to the substrate and one or more serializer/deserializer (SerDes) interfaces may connect the IC die to the one or more photonic modules. The IC die may be an application specific integrated circuit (ASIC) die and the one or more photonic modules may include a photonic integrated circuit (PIC) and fiber array. The one or more photonic modules may be mounted to one or more additional substrates which may be attached to the substrate via one or more sockets.

A CMOS compatible heterogeneously integrated material platform for photonic integrated circuitry is invented. The material platform has SiO2 as cladding material, at least a bottom layer made of moderate refractive index (contrast) material(s), a bonded single crystal Si layer transfer from either a SOI wafer or a ion implanted single crystal Si wafer ready for ion cut split on top of the bottom layer, and some devices enabling light coupling between the devices made within these two layers. The invention provides a great material platform to offer a full set of photonic building blocks for all sorts of different applications such as photonic circuitry for optical neural network, quantum computing, telecommunication, data communication, optical switching, optical sensing, passive and/or active Si optical interposer with its size even bigger than lithography step field.

A CMOS compatible heterogeneously integrated material platform for photonic integrated circuitry is invented. The material platform has SiO2 as cladding material, at least a bottom layer made of moderate refractive index (contrast) material(s), a bonded single crystal Si layer transfer from either a SOI wafer or a ion implanted single crystal Si wafer ready for ion cut split on top of the bottom layer, and some devices enabling light coupling between the devices made within these two layers. The invention provides a great material platform to offer a full set of photonic building blocks for all sorts of different applications such as photonic circuitry for optical neural network, quantum computing, telecommunication, data communication, optical switching, optical sensing, passive and/or active Si optical interposer with its size even bigger than lithography step field.

An example device in accordance with an aspect of the present disclosure includes an avalanche photodetector to enable carrier multiplication for increased responsivity, and a receiver based on source-synchronous CMOS and including adaptive equalization. The photodetector and receiver are monolithically integrated on a single chip.

A semiconductor chip, an optoelectronic device including a semiconductor chip, and a method for producing a semiconductor chip are disclosed. In an embodiment the chip includes a semiconductor body with a first main surface and a second main surface arranged opposite to the first main surface, wherein the semiconductor body includes a p-doped sub-region, which forms part of the first main surface, and an n-doped sub-region, which forms part of the second main surface and a metallic contact element that extends from the first main surface to the second main surface and that is electrically isolated from one of the sub-regions.