Patent classifications
H01L25/043
METHOD AND APPARATUS TO FACILITATE DIRECT SURFACE COOLING OF A CHIP WITHIN A 3D STACK OF CHIPS USING OPTICAL INTERCONNECT
In one embodiment, the disclosure relates to a system of stacked and connected layers of circuits that includes at least one pair of adjacent layers having very few physical (electrical) connections. The system includes multiple logical connections. The logical interconnections may be made with light transmission. A majority of physical connections may provide power. The physical interconnections may be sparse, periodic and regular. The exemplary system may include physical space (or gap) between the a pair of adjacent layers having few physical connections. The space may be generally set by the sizes of the connections. A constant flow of coolant (gaseous or liquid) may be maintained between the adjacent pair of layers in the space.
DIE-DIE STACKING
A method includes forming a stack of semiconductor die. The stack includes a first semiconductor die, a second semiconductor die and a third semiconductor die. The first semiconductor die is stacked above the second semiconductor die and the third semiconductor die is stacked above the first semiconductor die. A first optical transmitter and a first optical receiver are provided in the first semiconductor die, a second optical transmitter is provided in the second semiconductor die, and a second optical receiver is provided in the third semiconductor die. A first optical signal is transmitted from the first optical transmitter in the first semiconductor die to the second optical receiver in the third semiconductor die. A second optical signal is transmitted from the second optical transmitter in the second semiconductor die to the first optical receiver in the first semiconductor die.
PACKAGE-ON-PACKAGE (POP) TYPE SEMICONDUCTOR PACKAGES
Provided are package-on-package (POP)-type semiconductor packages including a lower package having a first size and including a lower package substrate in which a lower semiconductor chip is, an upper redistribution structure on the lower package substrate and the lower semiconductor chip, and alignment marks. The packages may also include an upper package having a second size smaller than the first size and including an upper package substrate and an upper semiconductor chip. The upper package substrate may be mounted on the upper redistribution structure of the lower package and electrically connected to the lower package, and the upper semiconductor chip may be on the upper package substrate. The alignment marks may be used for identifying the upper package, and the alignment marks may be below and near outer boundaries of the upper package on the lower package.
Solar cell, multi-junction solar cell, solar cell module, and solar power generation system
A solar cell of an embodiment includes: a substrate; an n-electrode; an n-type layer; a p-type light absorption layer which is a semiconductor of a Cu-based oxide; and a p-electrode. The n-electrode is disposed between the substrate and the n-type layer. The n-type layer is disposed between the n-electrode and the p-type light absorption layer. The p-type light absorption layer is disposed between the n-type layer and the p-electrode. The n-type layer is disposed closer to a light incident side than the p-type light absorption layer. The substrate is a single substrate included in the solar cell.
Multilevel semiconductor device and structure with oxide bonding
A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including a structure designed to conduct electromagnetic waves, where the second level is disposed above the first level, where the integrated circuits include single crystal transistors; and an oxide layer disposed between the first level and the second level, where the integrated circuits include at least one processor, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.
Semiconductor component having through-silicon vias
A semiconductor component includes a substrate having an opening. The semiconductor component further includes a first dielectric liner in the opening, wherein the first dielectric liner having a thickness T.sub.1 at a first end of the opening, and a thickness T.sub.2 at a second end of the opening, and R.sub.1 is a ratio of T.sub.1 to T.sub.2. The semiconductor component further includes a second dielectric liner over the first dielectric liner, wherein the second dielectric liner having a thickness T.sub.3 at the first end of the opening, a thickness T.sub.4 at the second end of the opening, R.sub.2 is a ratio of T.sub.3 to T.sub.4, and R.sub.1 is greater than R.sub.2.
INTELLIGENT SOLAR RACKING SYSTEM
According to one or more embodiments, an intelligent solar racking system is provided. The intelligent solar racking system includes a racking frame that receives and mechanically supports solar modules. The intelligent solar racking system includes sensors distributed throughout the racking frame. Each of the sensors detects and reports parameter data by generating output signals. The sensors include module sensors positioned to associate with each of the solar modules and detect a module presence as the parameter data for the solar modules. The intelligent solar racking system includes a computing device that receives, stores, and analyzes the output signals to determine and monitor operations of the intelligent solar racking system.
Light trapping dynamic photovoltaic module
There is provided a light trapping dynamic photovoltaic module having a module surface configured to be exposed to solar rays, including a plurality of photovoltaic cell stacks configured adjacent to each other throughout the module surface, wherein each photovoltaic cell stack comprises a plurality of photovoltaic cells. Further, a plurality of reflective strips are placed in between each of the photovoltaic cell stacks for continuously reflecting incident solar rays from one reflective strip to another until absorbed by a photovoltaic cell among said plurality of photovoltaic cells, wherein the incident solar rays are continuously reflected through a mirror phenomenon, wherein the incident solar rays are additionally reflected by front and back panels of the dynamic photovoltaic module, thereby trapping incident solar rays within boundaries of the dynamic photovoltaic module for conversion into electrical energy. Also disclosed is a method of manufacturing the light trapping photovoltaic module.
INTELLIGENT SOLAR RACKING SYSTEM
According to one or more embodiments, an intelligent solar racking system is provided. The intelligent solar racking system includes a racking frame that receives and mechanically supports solar modules. The intelligent solar racking system includes sensors distributed throughout the racking frame. Each of the sensors detects and reports parameter data by generating output signals. The sensors include module sensors positioned to associate with each of the solar modules and detect a module presence as the parameter data for the solar modules. The intelligent solar racking system includes a computing device that receives, stores, and analyzes the output signals to determine and monitor operations of the intelligent solar racking system.
Integrated photonic device manufacturing method
A photonic device manufacturing method, including a step of transfer, onto a same surface of a photonic circuit previously formed inside and on top of a first substrate, of at least a first die made up of a III-V semiconductor material and of at least a second die made up of silicon nitride, the method further including a step of forming of photonic components in said at least one first and at least one second dies.