An electrically conductive sub-collector layer is provided in a surface layer portion of a substrate. A collector layer, a base layer, and an emitter layer are located within the sub-collector layer when viewed in plan. The collector layer is connected to the sub-collector layer. An emitter electrode and a base electrode are long in a first direction when viewed in plan. The emitter electrode overlaps the emitter layer. The base electrode and the emitter electrode are discretely located away from each other in a second direction orthogonal to the first direction. A collector electrode is located on one side in the second direction with respect to the emitter electrode and is not located on the other side when viewed in plan. A base line is connected to the base electrode in a manner so as to adjoin a portion other than longitudinal ends of the base electrode.

An electrically conductive sub-collector layer is provided in a surface layer portion of a substrate. A collector layer, a base layer, and an emitter layer are located within the sub-collector layer when viewed in plan. The collector layer is connected to the sub-collector layer. An emitter electrode and a base electrode are long in a first direction when viewed in plan. The emitter electrode overlaps the emitter layer. The base electrode and the emitter electrode are discretely located away from each other in a second direction orthogonal to the first direction. A collector electrode is located on one side in the second direction with respect to the emitter electrode and is not located on the other side when viewed in plan. A base line is connected to the base electrode in a manner so as to adjoin a portion other than longitudinal ends of the base electrode.

In accordance with at least one embodiment, an ESD device comprises: a semiconductor; a pad; a ground rail; a p-well formed in the semiconductor; a first p-type region formed in the p-well and electrically coupled to the ground rail; a first n-type region formed in the p-well and electrically coupled to the pad; a second n-type region formed in the p-well and electrically coupled to the ground rail; an n-well formed in the semiconductor; a first n-type region formed in the n-well; a first p-type region formed in the n-well and electrically coupled to the pad; and a second p-type region formed in the n-well and electrically coupled to the first n-type region formed in the n-well.

A semiconductor module includes a high-side switching device and a low-side switching device that respectively form an upper arm and a lower arm, freewheeling diodes that are respectively connected to the switching devices in anti-parallel, and a high-side driver circuit and a low-side driver circuit that respectively switch the high-side switching device and the low-side switching device ON and OFF. In the upper arm, an anode electrode of the freewheeling diode and a reference voltage electrode of the high-side driver circuit are directly connected via a first wiring, and the anode electrode of the freewheeling diode is connected to a reference voltage electrode of the high-side switching device via a second wiring having an inductance.

Provided is a semiconductor device including a substrate having a P-type conductivity, a buried layer having an N-type conductivity, an NPN bipolar junction transistor (BJT), and a first well region having the P-type conductivity. The buried layer is located on the substrate. The NPN BJT is located on the buried layer. The first well region is located between the buried layer and the NPN BJT. The NPN BJT is separated from the buried layer by the first well region.

A semiconductor module includes a high-side switching device and a low-side switching device that respectively form an upper arm and a lower arm, freewheeling diodes that are respectively connected to the switching devices in anti-parallel, and a high-side driver circuit and a low-side driver circuit that respectively switch the high-side switching device and the low-side switching device ON and OFF. In the upper arm, an anode electrode of the freewheeling diode and a reference voltage electrode of the high-side driver circuit are directly connected via a first wiring, and the anode electrode of the freewheeling diode is connected to a reference voltage electrode of the high-side switching device via a second wiring having an inductance.

In accordance with at least one embodiment, an ESD device comprises: a semiconductor; a pad; a ground rail; a p-well formed in the semiconductor; a first p-type region formed in the p-well and electrically coupled to the ground rail; a first n-type region formed in the p-well and electrically coupled to the pad; a second n-type region formed in the p-well and electrically coupled to the ground rail; an n-well formed in the semiconductor; a first n-type region formed in the n-well; a first p-type region formed in the n-well and electrically coupled to the pad; and a second p-type region formed in the n-well and electrically coupled to the first n-type region formed in the n-well.

Provided is a semiconductor device including a substrate having a P-type conductivity, a buried layer having an N-type conductivity, an NPN bipolar junction transistor (BJT), and a first well region having the P-type conductivity. The buried layer is located on the substrate. The NPN BJT is located on the buried layer. The first well region is located between the buried layer and the NPN BJT. The NPN BJT is separated from the buried layer by the first well region.