A memory device is disclosed, including a bit cell storing a bit data. The bit cell includes multiple first transistors coupled to a node, multiple second transistors each coupled in series to a corresponding one of the first transistors, and at least one third transistor. The first transistors are turned on in response to a control signal. The second transistors are turned on in response to a first word line signal. The at least one third transistor has a control terminal to receive a second word line signal. In a programming mode of the memory device, the at least one third transistor provides, in response to the second word line signal, an adjust voltage to the node. The adjust voltage is associated with a voltage level of a first terminal of the at least one third transistor.

An ESD protection circuit includes a trigger transistor that is responsive to a detection signal indicating an ESD event. The trigger transistor pulls the voltage of a hold node towards a voltage of a power supply rail in response to the detection signal indicating an ESD event. The ESD protection circuit includes a replica trigger transistor whose leakage current controls current provided to the hold node after the detection signal no longer indicates an ESD event to compensate for leakage current through the trigger transistor.

A system and method for combining positive and negative voltage electrostatic discharge (ESD) protection into a clamp that uses cascoded circuitry, including detecting, by an electrostatic discharge protection system, a voltage pulse on an input pin of an integrated circuit (IC) controller, the IC controller coupled between a power supply node and a ground supply node; determining, by the ESD protection circuit, an ESD event on the input pin based on the voltage detected on the input pin; and/or controlling, by the ESD protection circuit during the ESD event, one or more clamps to transport the voltage pulse from the input pin of the IC controller to the power supply node.

Various apparatuses, systems, methods, and media are disclosed to provide over-voltage protection to a data interface of a multi-protocol memory card that includes a first communication interface and a second communication interface that enable communication using different protocols. An interface voltage protection circuit includes a control circuit configured to receive a first supply voltage for operating the first communication interface. The interface voltage protection circuit further includes a pull-down circuit operatively connected with the control circuit, configured to pull down a voltage at a supply voltage rail of the second communication interface such that a voltage at a plurality of connector terminals of the second communication interface is lower than the first supply voltage.

A device includes standard cells in a layout of an integrated circuit, the standard cells includes first and second standard cells sharing a first active region and a second active region. The first standard cell includes first and second gates. The first gate includes a first gate finger and a second gate finger that are arranged over the first active region, for forming the first transistor and the second transistor. The second gate is separate from the first gate, the second gate includes a third gate finger and a fourth gate finger that are arranged over the second active region, for forming the third transistor and the fourth transistor. The second standard cell includes a third gate arranged over the first active region and the second active region, for forming the fifth transistor and the sixth transistor. The first to fourth transistors operate as an electrostatic discharge protection circuit.

An embodiment of the present disclosure relates to an electronic circuit including a first switch coupling a first node of the circuit to an input/output terminal of the circuit; a second switch coupling the first node to a second node of application of a fixed potential; and a high-pass filter having an input coupled to the terminal and an output coupled to a control terminal of the second switch.

In the examples provided herein, an electrostatic discharge (ESD) recording circuit has a first memristive element coupled to a pin of an integrated circuit. The first memristive element switches from a first resistance to a second resistance when an ESD event occurs at the pin, and the first resistance is less than the second resistance. The ESD recording circuit also has shunting circuitry to shunt energy from an additional ESD event away from the first memristive element.

The present disclosure is directed to a semiconductor device and a manufacturing method thereof, which relate to the field of semiconductor technologies. The semiconductor device includes a fin ESD element. The method includes: providing a substrate structure, where the substrate structure includes a semiconductor substrate, and a semiconductor fin for the fin ESD element and an electrode structure surrounding a part of the semiconductor fin that are on the semiconductor substrate; forming a second dielectric layer on the substrate structure to cover the electrode structure; forming, in the second dielectric layer, a trench extending to a top of the electrode, where the trench is on the electrode and extends along a longitudinal direction of the electrode, and a transverse width of the trench is less than or equal to a transverse width of the top of the electrode; and filling the trench with a metal material, so as to form a metal heat sink that is on the top of the electrode and is coupled to the electrode. With the present disclosure, an existing structure of an ESD element is improved, so that a metal heat sink can effectively improve a head dissipation effect of a device, thereby improving a performance of the device.

Embodiments of the invention provide an array substrate, a display device and a manufacturing method of the array substrate. The array substrate comprises a substrate (10) and a plurality of electrostatic discharge short-circuit rings (20) provided on the substrate. Each of the electrostatic discharge short-circuit rings (20) comprises a gate electrode (22), a gate insulating layer (26), an active layer (21), a source electrode (23), a drain electrode (24) and a passivation layer (30). Each of the electrostatic discharge short-circuit ring (20) further comprises a transparent conductive layer (25) for connecting the gate electrode (22) and the drain electrode (24), and the transparent conductive layer (25) is provided below the passivation layer (30).

Electrostatic discharge (ESD) protection is provided in circuits which use of a tunneling field effect transistor (TFET) or an impact ionization MOSFET (IMOS). These circuits are supported in silicon on insulator (SOI) and bulk substrate configurations to function as protection diodes, supply clamps, failsafe circuits and cutter cells. Implementations with parasitic bipolar devices provide additional parallel discharge paths.