A semiconductor integrated circuit device may include a first region, a second region, a pad structure and an electrostatic discharge (ESD) connection. The first region may be positioned adjacent to a semiconductor substrate. An ESD protection circuit may be integrated in the first region. The second region may be stacked on the first region. A plurality of memory cells may be formed in the second region. The pad structure may be arranged over the second region to receive an external voltage. The ESD connection may include a plurality of lower conductive wirings in the first region. At least one of the lower conductive wirings may be electrically connected with the ESD protection circuit. The at least one of the lower conductive wirings may be drawn to a portion corresponding to the pad structure.

Disclosed is a circuit arrangement. The circuit arrangement includes: an electronic circuit integrated in a semiconductor body; an input pin coupled to the electronic circuit; an insulation layer formed on top of the semiconductor body; and a protection device connected to the input pin. The protection device is integrated in a polysilicon layer formed on top of the insulation layer.

The present disclosure provides an electrostatic discharge (ESD) protection structure, an ESD protection circuit, and a chip. The ESD protection structure includes a semiconductor substrate, a first N-type well, a first P-type well, a first N-type doped portion, a first P-type doped portion, a second N-type doped portion, and a second P-type doped portion. The semiconductor substrate includes a first integrated region. The first N-type well is located in the first integrated region. The first P-type well is located in the first integrated region. The first N-type doped portion is located in the first N-type well. The first P-type doped portion is located in the first N-type well. The second N-type doped portion is located in the first P-type well. The second P-type doped portion is located on a side of the second N-type doped portion away from the first N-type well.

A device includes standard cells in a layout of an integrated circuit, the standard cells includes first and second standard cells sharing a first active region and a second active region. The first standard cell includes first and second gates. The first gate includes a first gate finger and a second gate finger that are arranged over the first active region, for forming the first transistor and the second transistor. The second gate is separate from the first gate, the second gate includes a third gate finger and a fourth gate finger that are arranged over the second active region, for forming the third transistor and the fourth transistor. The second standard cell includes a third gate arranged over the first active region and the second active region, for forming the fifth transistor and the sixth transistor. The first to fourth transistors operate as an electrostatic discharge protection circuit.

An integrated circuit device having insulated gate field effect transistors (IGFETs) having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure has been disclosed. The integrated circuit device may include electrostatic discharge (ESD) protection circuit structures. The ESD protection circuit structures may be formed in regions other than the region that the IGFETs are formed as well as in the region that the IGFETs having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure are formed. By forming ESD protection circuit structures in regions below the IGFETs, an older process technology may be used and device size may be decreased. Furthermore, planar IGFETs of FinFETs may be formed in other regions to decrease device size and improve costs.

Methods of forming a capacitor structure might include forming a first and second conductive regions having first and second conductivity types, respectively, in a semiconductor material, forming a dielectric overlying the first and second conductive regions, forming a conductor overlying the dielectric, and patterning the conductor, the dielectric, and the first and second conductive regions to form a first island of the first conductive region, a second island of the first conductive region, an island of the second conductive region, a first portion of the dielectric overlying the first island of the first conductive region separated from a second portion of the dielectric overlying the second island of the first conductive region and the island of the second conductive region, and a first portion of the conductor overlying the first portion of the dielectric separated from a second portion of the conductor overlying the second portion of the dielectric.

In accordance with an embodiment, a semiconductor device includes: an n-doped region disposed over an insulating layer; a p-doped region disposed over the insulating layer adjacent to the n-doped region, where an interface between the n-doped region and the p-doped region form a first diode junction; a plurality of segmented p-type anode regions disposed over the insulating layer, each of the plurality of segmented p-type anode regions being surrounded by the n-doped region, where a doping concentration of the plurality of segmented p-type anode regions is greater than a doping concentration of the p-doped region; and a plurality of segmented n-type cathode regions disposed over the insulating layer. Each of the plurality of segmented n-type cathode regions are surrounded by the p-doped region, where a doping concentration of the plurality of segmented n-type cathode regions is greater than a doping concentration of the n-doped region.

An electronic device including a first substrate, a semiconductor layer, a second substrate and a color filter is disclosed. The first substrate has a peripheral region. The semiconductor layer is disposed on the first substrate in the peripheral region. The second substrate is opposite to the first substrate. The color filter is disposed between the first substrate and the second substrate and in the peripheral region of the first substrate, and the color filter overlaps the semiconductor layer.

The present disclosure provides an electrostatic protection device, and relates to the technical field of semiconductors. The electrostatic discharge protection device includes a first P-type heavily-doped region, a first N-type heavily-doped region, a second N-type heavily-doped region, a second P-type heavily-doped region, and a third N-type heavily-doped region. The first P-type heavily-doped region and the first N-type heavily-doped region are located in a P well, the second P-type heavily-doped region and the third N-type heavily-doped region are located in a first N well, one part of the second N-type heavily-doped region is located in the P well, the other part of the second N-type heavily-doped region is located in first N well, and the P well and the first N well are adjacent to each other and both located in the P-type substrate.

An electrostatic discharge (ESD), protection device is provided. In accordance with the present disclosure, an ESD protection device is provided that includes a series connection of a first unit having strong snapback and low series capacitance and a second high-voltage unit that displays a relatively high holding/trigger voltage to ensure latch up and improper triggering of the ESD protection device while at the same time providing high-voltage operation with low capacitive loading.