A vertical thyristor memory array including: a vertical thyristor memory cell, the vertical thyristor memory cell including: a p+ anode; an n-base located below the p+ anode; a p-base located below the n-base; a n+ cathode located below the p-base; an isolation trench located around the vertical thyristor memory cell; an assist gate located in the isolation trench adjacent the n-base wherein an entire vertical height of the assist gate is positioned within an entire vertical height of the n-base.

A memory device, an operating method of the memory device, and a fabricating method of the memory device are provided. A memory device includes: a semiconductor column extending vertically on a substrate and including a source region of a first conductivity type, an intrinsic region, and a drain region of a second conductivity type; a first gate electrode disposed adjacent to the drain region to cover the intrinsic region; a second gate electrode spaced apart from the first gate electrode and disposed adjacent to the source region to cover the intrinsic region; a first gate electrode disposed between the first gate electrode and the intrinsic region; and a second gate insulating layer disposed between the second gate electrode and the intrinsic region.

A bidirectional power semiconductor device with full turn-off control in both current directions and improved electrical and thermal properties is provided, the device comprises a plurality of first gate commutated thyristor (GCT) cells and a plurality of second GCT cells alternating with each other, a first base layer of each first GCT cell is separated from a neighbouring second anode layer of a neighbouring second GCT cell by a first separation region, and a second base layer of each second GCT cell is separated from a neighbouring first anode layer of a neighbouring first GCT cell by a second separation region.

Methods and systems for reducing electrical disturb effects between thyristor memory cells in a memory array are provided. Electrical disturb effects between cells are reduced by using a material having a reduced minority carrier lifetime as a cathode line that is embedded within the array. Disturb effects are also reduced by forming a potential well within a cathode line, or a one-sided potential barrier in a cathode line.

Electrical overstress protection for electronic systems subject to electromagnetic compatibility fault conditions are provided herein. In certain implementations, a stacked thyristor protection structure with a high holding voltage includes a protection device having a trigger voltage and a holding voltage. A trigger voltage of the stacked thyristor protection structure is substantially equal to the trigger voltage of the protection device. The stacked thyristor protection structure further includes at least one resistive thyristor electrically connected to the protection device and operable to increase a holding voltage of the stacked thyristor protection structure relative to the holding voltage of the protection device. The at least one resistive thyristor comprising a PNP bipolar transistor and a NPN bipolar transistor that are cross-coupled, and a conductor connecting a collector of the PNP bipolar transistor to a collector of the NPN bipolar transistor.

A thyristor tile includes first and second PNP tiles and first and second NPN tiles. Each PNP tile is adjacent to both NPN tiles, and each NPN tile is adjacent to both PNP tiles. A thyristor includes a plurality of PNP tiles and a plurality of NPN tiles. The PNP and NPN tiles are arranged in an alternating configuration in both rows and columns. The PNP tiles are oriented perpendicular to the NPN tiles. Interconnect layers have a geometry that enables even distribution of signals to the PNP and NPN tiles.

A thyristor tile includes first and second PNP tiles and first and second NPN tiles. Each PNP tile is adjacent to both NPN tiles, and each NPN tile is adjacent to both PNP tiles. A thyristor includes a plurality of PNP tiles and a plurality of NPN tiles. The PNP and NPN tiles are arranged in an alternating configuration in both rows and columns. The PNP tiles are oriented perpendicular to the NPN tiles. Interconnect layers have a geometry that enables even distribution of signals to the PNP and NPN tiles.

Isolation between vertical thyristor memory cells in an array is improved with isolation regions between the vertical thyristor memory cells. The isolation regions are formed by electrically isolating cores surrounded by insulating material, such as silicon dioxide, in trenches between the memory cells. The electrically isolating cores may be tubes of air or conducting rods. Methods of constructing the isolation regions in a processes for manufacturing vertical thyristor memory cell arrays are also disclosed.

A light-emitting component includes: a substrate; plural light-emitting elements that are disposed on the substrate and that emit light in a direction intersecting with a surface of the substrate; and plural thyristors that are stacked on the plural light-emitting elements and that are turned ON to drive the corresponding light-emitting elements so that the light-emitting elements emit light or an amount of light emitted from the light-emitting elements is increased. Each of the plural light-emitting elements includes a current confinement region which is oxidized via a hole provided in a multilayer structure. The multilayer structure is constituted by a corresponding light-emitting element and a corresponding thyristor.

Electrical overstress protection for electronic systems subject to electromagnetic compatibility fault conditions are provided herein. In certain implementations, a stacked thyristor protection structure with a high holding voltage includes a protection device having a trigger voltage and a holding voltage. A trigger voltage of the stacked thyristor protection structure is substantially equal to the trigger voltage of the protection device. The stacked thyristor protection structure further includes at least one resistive thyristor electrically connected to the protection device and operable to increase a holding voltage of the stacked thyristor protection structure relative to the holding voltage of the protection device. The at least one resistive thyristor comprising a PNP bipolar transistor and a NPN bipolar transistor that are cross-coupled, and a conductor connecting a collector of the PNP bipolar transistor to a collector of the NPN bipolar transistor.