A method includes forming a pad layer and a mask layer over a substrate; patterning the mask layer, the pad layer, and the substrate to form pads, masks, and first and semiconductor fins over the substrate; forming a liner covering the pads, the masks, and the first and second semiconductor fins; removing a first portion of the liner to expose sidewalls of the first semiconductor fin, while leaving a second portion of the liner covering sidewalls of the second semiconductor fin; forming an isolation material over the substrate; and performing a CMP process to the isolation material until a first one of the pads over the second semiconductor fin is exposed; and etching back the isolation material and the second portion of the liner.

An apparatus includes a first drain/source region and a second drain/source region surrounded by an isolation ring formed over a substrate, the isolation ring formed being configured to be floating, and a first diode connected between the substrate and the isolation ring, wherein the first diode is a Schottky diode.

The present disclosure relates to a latch-up test structure, including: a substrate of a first conductive type; a first well region of a second conductive type, located in the substrate of the first conductive type; a first doped region of the first conductive type, located in the first well region of the second conductive type; a first doped region of the second conductive type, located in the first well region of the second conductive type; and a second doped region of the first conductive type, a second doped region of the second conductive type, a third doped region of the first conductive type, and a third doped region of the second conductive type that are arranged at intervals in the substrate of the first conductive type.

A method for identifying a latch-up structure includes the following operations. In a chip layout, a first P-type heavily doped region connected to a ground pad and located in a P-type substrate is found, and a first N-type heavily doped region connected to a power pad and located in an N-well is found. A second N-type heavily doped region adjacent to the first P-type heavily doped region and located in the P-type substrate is found. A second P-type heavily doped region adjacent to the first N-type heavily doped region and located in the N-well is found, the N-well is located on the P-type substrate. An area that is formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the N-well, and the P-type substrate is identified as the latch-up structure.

The present disclosure provides a latch-up test structure, including: a substrate of a first conductive type; a first well region of the first conductive type, located in the substrate of the first conductive type; a first doped region of the first conductive type, located in the first well region of the first conductive type; a first doped region of a second conductive type, located in the first well region of the first conductive type; and a second doped region of the first conductive type, a second doped region of the second conductive type, a third doped region of the first conductive type, and a third doped region of the second conductive type that are arranged at intervals in the substrate of the first conductive type.

A method for identifying a latch-up structure includes the following: in a chip layout, a first N-type heavily doped region connected to a first input/output pad and located in a P-type substrate is found; a first P-type heavily doped region located in an N-well and a second P-type heavily doped region located in the P-type substrate, both of which are adjacent to the first N-type heavily doped region, are found; a second N-type heavily doped region adjacent to the first P-type heavily doped region and located in the N-well is found, wherein the N-well is located on the P-type substrate; and an area formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the N-well and the P-type substrate is identified as the latch-up structure.

A method of biasing a guard ring structure includes biasing a gate of a MOS transistor to a first bias voltage level, biasing first and second S/D regions of the MOS transistor to a power domain voltage level, biasing a gate of the guard ring structure to a second bias voltage level, and biasing first and second heavily doped regions of the guard ring structure to the power domain voltage level. Each of the first and second S/D regions has a first doping type, each of the first and second heavily doped regions has a second doping type different from the first doping type, and each of the first and second S/D regions and the first and second heavily doped regions is positioned in a substrate region having the second doping type.

Embodiments described herein may be related to apparatuses, processes, and techniques related to well biasing using a buried power rail (BPR) within a circuit structure. Embodiments include using a silicide material between the BPR and a well, where the silicide material provides ohmic contact between the BPR and the well. Other embodiments may be described and/or claimed.

An integrated circuit includes a first semiconductor well contained in a semiconductor substrate and a second semiconductor well contained in the first semiconductor well. A capacitive element for the integrated circuit includes a first electrode and a second electrode, where the first electrode includes at least one vertical conductive structure filling a trench extending vertically into the first semiconductor well. The vertical conductive structure is electrically isolated from the first semiconductor well by a dielectric envelope covering a base and the sides of the trench. The vertical conductive structure penetrates into the second semiconductor well at least at one longitudinal end of the trench. The second electrode includes the first semiconductor well and the second semiconductor well.

The present disclosure relates to an integrated chip. The integrated chip includes a source region and a drain region disposed within an upper surface of a substrate. One or more dielectric materials are disposed within a trench defined by sidewalls of the substrate that surround the source region and the drain region. The one or more dielectric materials include one or more interior surfaces defining a recess within the one or more dielectric materials. A gate structure is disposed over the substrate between the source region and the drain region. The gate structure includes a first gate material over the upper surface of the substrate and a second gate material. The second gate material completely fills the recess as viewed along a cross-sectional view.