An array substrate includes a gate layer, a first insulating layer, a channel layer, a source-drain layer, a second insulating layer, and a common electrode layer that are sequentially stacked, wherein the second insulating lay is provided with via holes formed therein; and the source-drain layer includes a plurality of sources, a plurality of drains, a plurality of data lines and a plurality of common electrode signal lines. The common electrode signal line includes a plurality of common electrode signal line segments, each of the common electrode signal line segments passes through at least one sub-pixel row, and each of the common electrode signal line segments is connected to the common electrode layer through the via hole.

An organic light-emitting diode (OLED) display panel and a method for manufacturing the same are provided. The OLED display panel at least includes a thin film transistor (TFT) array substrate, a passivation layer, a planarization layer, and planarization-compensating layer. The planarization layer has a first planarization part corresponding to a light-emitting area, and a second planarization part corresponding to a defining area and a part of the light-emitting area. Height of a surface of the planarization-compensating layer from the surface of the TFT array substrate and height of a surface of the second planarization part from the surface of the TFT array substrate are level.

An organic light-emitting diode (OLED) display panel and a method for manufacturing the same are provided. The OLED display panel at least includes a thin film transistor (TFT) array substrate, a passivation layer, a planarization layer, and planarization-compensating layer. The planarization layer has a first planarization part corresponding to a light-emitting area, and a second planarization part corresponding to a defining area and a part of the light-emitting area. Height of a surface of the planarization-compensating layer from the surface of the TFT array substrate and height of a surface of the second planarization part from the surface of the TFT array substrate are level.

A COA substrate manufacturing method including: forming a TFT on a base substrate; forming a second insulation layer on the TFT; forming a color resist layer on the second insulation layer; forming a third insulation layer on the color resist layer; forming a through hole which exposes the drain electrode of the TFT; forming an ITO film layer on the third insulation layer; forming a photoresist layer on the ITO film layer; performing a light-shielding process to the photoresist layer on the vias-region ITO film layer and an exposure process to the photoresist layer on the non vias-region ITO film layer; developing the photoresist layer on the vias-region ITO and the non vias-region ITO film layers to obtain a photoresist layer plug covered on the vias-region ITO film layer. The photoresist is provided to fill the through hole so as to improve the quality of a display device.

An array substrate includes a display area and a peripheral area adjacent to the display area; the display area includes a plurality of pixel units; each pixel unit includes a thin-film transistor (TFT) and a pixel electrode; and a drain electrode of the TFT directly contacts with the pixel electrode. In the array substrate, the drain electrode of the TFT directly contacts with the pixel electrode, and hence a uniformly distributed electric field will be generated between common electrodes and the pixel electrodes.

The present disclosure provides a display substrate assembly including a first substrate and a second substrate opposite to each other, the first substrate including a first region and a second region, and, a total thickness of functional layers within the first region being less than a total thickness of functional layers within the second region, of the first substrate. A thickness compensation layer is provided on at least one of the first substrate and the second substrate, a position of the thickness compensation layer corresponds to a position of the first region, and, a sum of thickness of a thickness of the thickness compensation layer and the total thickness of the functional layers within the first region equals to the total thickness of the functional layers within the second region.

A method for producing an array substrate is provided. The method includes: forming metal film layers and patterning the metal film layers to form a plurality rows of gate lines and a plurality columns of data lines crossed to each other in the non-display area and forming thin film transistors; forming a pad part at one end of the gate lines or data lines. The process of producing the pad part includes: forming a first insulation layer on the metal film layers by patterning; forming an etching protection layer, a source and drain metal layer and a second insulation layer sequentially by patterning, wherein the first insulation layer, the etching protection layer, the source and drain metal layer and the second insulation layer form a trapezoid stack.

The present disclosure provides a display backplane, a method for preparing the same, and a display device. The display backplane includes a substrate, an electronic device and an alignment mark arranged on the substrate, and a filling layer, the filling layer being filled in at least a part of a recessed area located on a surface of the substrate away from the electronic device, and a minimum distance between an orthogonal projection of the at least part of the recessed area on the substrate and an orthogonal projection of the alignment mark on the substrate being less than 200 μm.

The present disclosure provides an array substrate and a method of manufacturing the same, and a display device comprising the array substrate. The array substrate comprises: a substrate; gate lines and data lines arranged to intersect one another on the substrate; a gate line connection conducting wire layer provided between the gate lines and the substrate and below the gate lines; and/or, a data line connection conducting wire layer provided in regions of the array substrate corresponding to the data lines; wherein the gate line connection conducting wire layer is electrically isolated from the data line connection conducting wire layer.

A liquid crystal display device includes a TFT substrate having a first alignment film and an opposing substrate having a second alignment film with liquid crystals sandwiched therebetween. One of the first and second alignment films, comprises a first polyimide produced via polyamide acid ester containing cyclobutane as a precursor and a second polyimide produced via polyamide acid as a precursor. The polyamide acid has a higher polarity than that of the polyamide acid ester. The one of the first and second alignment films is responsive to photo-alignment. A first side of the one of the first and second alignment films is adjacent to the liquid crystals, and a second side thereof is closer to one of the TFT substrate and the counter substrate than the first side. The first side contains more of the first polyimide and less of the second polyimide than the second side.