The invention relates to a lateral field effect transistor, in particular a HEMT having a heterostructure, in a III/V semiconductor system with a p-type semiconductor being arranged between an ohmic load contact, in particular a drain contact, and a gate contact of the transistor for an injection of holes into a portion of the transistor channel. Further, a recombination zone implemented by a floating ohmic contact is provided for to improve the device performance.

The present disclosure provides a semiconductor structure and a manufacturing method therefor. In the semiconductor structure, a semiconductor substrate, a heterojunction and an in-situ insulation layer are disposed from bottom to top, a trench is provided in the in-situ insulation layer, and a transition layer is located on at least an in-situ insulation layer, the p-type semiconductor layer is located in the trench and on the gate region of the transition layer, and the heavily doped n-type layer is located on at least one of the p-type semiconductor layer in the gate region, the source region of the heterojunction, or the drain region of the heterojunction.

We disclose a III-nitride semiconductor based heterojunction power device comprising: a first heterojunction transistor formed on a substrate, the first heterojunction transistor comprising: a first III-nitride semiconductor region formed over the substrate, wherein the first III-nitride semiconductor region comprises a first heterojunction comprising at least one two dimensional carrier gas; a first terminal operatively connected to the first III-nitride semiconductor region; a second terminal laterally spaced from the first terminal and operatively connected to the first III-nitride semiconductor region; a first plurality of highly doped semiconductor regions of a first polarity formed over the first III-nitride semiconductor region, the first plurality of highly doped semiconductor regions being formed between the first terminal and the second terminal; a first gate region operatively connected to the first plurality of highly doped semiconductor regions; and a second heterojunction transistor formed on the substrate. The second heterojunction transistor comprises: a second III-nitride semiconductor region formed over the substrate, wherein the second III-nitride semiconductor region comprises a second heterojunction comprising at least one two dimensional carrier gas; a third terminal operatively connected to the second III-nitride semiconductor region; a fourth terminal laterally spaced from the third terminal in the first dimension and operatively connected to the second III-nitride semiconductor region; a second gate region being formed over the second III-nitride semiconductor region, and between the third terminal and the fourth terminal. One of the first and second heterojunction transistors is an enhancement mode field effect transistor and the other of the first and second heterojunction transistors is a depletion mode field effect transistor.

Provided herein are a wide-bandgap semiconductor bipolar charge trapping (BCT) non-volatile memory structure with only one single insulating layer and a fabrication method thereof. Monolithically integrated enhancement-mode (E-mode) n-channel and p-channel field effect transistors (n-FETs and p-FETs) for gallium nitride (GaN)-based complementary logic (CL) gates based on the proposed memory structure, together with a fabrication method thereof in a single process run and various logic circuits incorporating one or more of the GaN-based CL gates, are also provided herein.

Gallium nitride (GaN) integrated circuit technology is described. In an example, an integrated circuit structure includes a substrate including silicon, the substrate having a top surface. A first trench is in the substrate, the first trench having a first width. A second trench is in the substrate, the second trench having a second width less than the first width. A first island is in the first trench, the first island including gallium and nitrogen and having first corner facets below the top surface of the substrate. A second island is in the second trench, the second island including gallium and nitrogen and having second corner facets below the top surface of the substrate.

A semiconductor thin film structure may include a substrate, a buffer layer on the substrate, and a semiconductor layer on the buffer layer, such that the buffer layer is between the semiconductor layer and the substrate. The buffer layer may include a plurality of unit layers. Each unit layer of the plurality of unit layers may include a first layer having first bandgap energy and a first thickness, a second layer having second bandgap energy and a second thickness, and a third layer having third bandgap energy and a third thickness. One layer having a lowest bandgap energy of the first, second, and third layers of the unit layer may be between another two layers of the first, second, and third layers of the unit layer.

A semiconductor body having a base carrier portion and a type III-nitride semiconductor portion is provided. The type III-nitride semiconductor portion includes a heterojunction and two-dimensional charge carrier gas. One or more ohmic contacts are formed in the type III-nitride semiconductor portion, the ohmic contacts forming an ohmic connection with the two-dimensional charge carrier gas. A gate structure is configured to control a conductive state of the two-dimensional charge carrier gas. Forming the one or more ohmic contacts comprises forming a structured laser-reflective mask on the upper surface of the type III-nitride semiconductor portion, implanting dopant atoms into the upper surface of the type III-nitride semiconductor portion, and performing a laser thermal anneal that activates the implanted dopant atoms.

A method for manufacturing nitride semiconductor device includes a second step of forming, on a gate layer material film, a gate electrode film that is a material film of a gate electrode, a third step of selectively etching the gate electrode film to form the gate electrode 22 of a ridge shape, and a fourth step of selectively etching the gate layer material film to form a semiconductor gate layer 21 of a ridge shape with the gate electrode 22 disposed at a width intermediate portion of a front surface thereof. The third step includes a first etching step for forming a first portion 22A from an upper end to a thickness direction intermediate portion of the gate electrode 22 and a second etching step being a step differing in etching condition from the first etching step and being for forming a remaining second portion 22B of the gate electrode.

A nitride semiconductor device includes a first nitride semiconductor layer, a second nitride semiconductor layer formed on the first nitride semiconductor layer, a third nitride semiconductor layer that is disposed on the second nitride semiconductor layer, has a ridge portion at least at a portion thereof, and contains an acceptor type impurity, a gate electrode that is disposed on the ridge portion, and a source electrode and a drain electrode that, on the second nitride semiconductor layer, are disposed across the ridge portion from each other, and has an active region and a nonactive region. The nonactive region has a first region and a film thickness of the second nitride semiconductor layer in the first region differs from a film thickness of the second nitride semiconductor layer in a region of the active region in which the ridge portion, the source electrode, and the drain electrode are not formed.

A semiconductor device includes a junction field effect transistor (JFET) including a source electrode, a drain electrode, and a gate electrode, and a metal oxide semiconductor field effect transistor (MOSFET) including a source electrode, a drain electrode, and a gate electrode. The JFET and the MOSFET are cascode-connected such that the source electrode of the JFET and the drain electrode of the MOSFET are electrically connected. A gate voltage dependency of the JFET or a capacitance ratio of a mirror capacitance of the MOSFET to an input capacitance of the MOSFET is adjusted in a predetermined range.