A layer structure for a normally-off transistor has an electron-supply layer made of a group-III-nitride material, a back-barrier layer made of a group-III-nitride material, a channel layer between the electron-supply layer and the back-barrier layer, made of a group-III-nitride material having a band-gap energy that is lower than the band-gap energies of the other layer mentioned. The material of the back-barrier layer is of p-type conductivity, while the material of the electron-supply layer and the material of the channel layer are not of p-type conductivity, the band-gap energy of the electron-supply layer is smaller than the band-gap energy of the back-barrier layer. In absence of an external voltage a lower conduction-band-edge of the third group-III-nitride material in the channel layer is higher in energy than a Fermi level of the material in the channel layer.

A semiconductor structure (100) comprising: a substrate (102), a first layer (106) of Al.sub.XGa.sub.YIn.sub.(1−X−Y)N disposed on the substrate, stacks (107, 109) of several second and third layers (108, 110) alternating against each other, between the substrate and the first layer, a fourth layer (112) of Al.sub.XGa.sub.YIn.sub.(1−X−Y)N, between the stacks, a relaxation layer of AlN disposed between the fourth layer and one of the stacks, and, in each of the stacks: the level of Ga of the second layers increases from one layer to the next in a direction from the substrate to the first layer, the level of Ga of the third layers is constant or decreasing from one layer to the next in said direction, the average mesh parameter of each group of adjacent second and third layers increasing from one group to the next in said direction, the thickness of the second and third layers is less than 5 nm.

The present disclosure relates to an integrated chip. The integrated chip includes a first III-V semiconductor material over a substrate and a second III-V semiconductor material over the first III-V semiconductor material. The second III-V semiconductor material is a different material than the first III-V semiconductor material. A doped region has a horizontally extending segment and one or more vertically extending segments protruding vertically outward from the horizontally extending segment. The horizontally extending segment is arranged below the first III-V semiconductor material.

Disclosed are an epitaxial structure of a semiconductor device, a manufacturing method, and a semiconductor device. The epitaxial structure includes a substrate and a semiconductor layer; the semiconductor layer includes a buffer layer; the buffer layer includes a first buffer subsection and a second buffer subsection which are connected to each other and arranged along a direction from a source preset region to a drain preset region, and a vertical projection on the substrate of the first buffer subsection overlaps with a vertical projection on the substrate of the source preset region, and a vertical projection on the substrate of the second buffer subsection overlaps with a vertical projection on the substrate of each of the gate preset region and the drain preset region; an ion implant concentration in the second buffer subsection is greater than or equal to an ion implant concentration in the first buffer subsection.

Structures for suppressing parasitic acoustic waves in semiconductor structures and integrated circuit devices are described. Such integrated circuit devices can, typically, produce undesirable acoustic wave resonances, and the acoustic waves can degrade the performance of the devices. In that context, some embodiments described herein relate to spoiling a conductive path that participates in the generation of acoustic waves. Some embodiments relate to spoiling acoustic characteristics of an acoustic resonant structure that may be present in the vicinity of the device. Combined embodiments that spoil the conductive path and acoustic characteristics are also possible.

The present disclosure relates to semiconductor power devices, and in particular, to a high-electron-mobility transistor (HEMT) with high voltage endurance capability and a preparation method thereof. The high-electron-mobility transistor with high voltage endurance capability includes a gate electrode, a source electrode, a drain electrode, a barrier layer, a P-type nitride semiconductor layer and a substrate, wherein the P-type nitride semiconductor layer is between the barrier layer and the substrate, which is insufficient to significantly deplete a two-dimensional electron gas in a channel except a gate stack, the source electrode is in electrical contact with the P-type nitride semiconductor layer, and the source electrode and the drain electrode are both in electrical contact with the two-dimensional electron gas.

The present disclosure provides a non-planar hole channel transistor and a fabrication method thereof. The non-planar hole channel transistor has a substrate, and a surface of the substrate has a step structure comprising a vertical surface. A non-planar channel layer is epitaxially grown laterally with the vertical surface as a core. A barrier layer is formed on the channel layer, so as to simultaneously form a two-dimensional hole gas and/or a two-dimensional electron gas at an interface between the barrier layer and the channel layer.

Embodiments of the present application disclose a semiconductor device and a manufacturing method thereof. The semiconductor device includes a semiconductor layer, a first doped nitride semiconductor layer disposed on the semiconductor layer, and a second doped nitride semiconductor layer disposed on the first doped nitride semiconductor layer. The semiconductor device further includes an undoped nitride semiconductor layer between the semiconductor layer and the first doped nitride semiconductor layer. The undoped nitride semiconductor layer has a first surface in contact with the semiconductor layer and a second surface in contact with the first doped nitride semiconductor layer.

A semiconductor device includes a nucleation layer, a buffer layer, a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, S/D electrodes, and a gate electrode. The nucleation layer includes a composition that includes a first element. The buffer layer includes a III-V compound which includes the first element. The buffer layer is disposed on and forms an interface with the nucleation layer. The buffer layer has a concentration of the first element oscillating within the buffer layer, such that the concentration of the first element varies as an oscillating function of a distance within a thickness of the buffer layer. Spacings among adjacent peaks of the oscillating function change from wide to narrow with respect to a first reference point within the buffer layer. The first and second nitride-based semiconductor layer, S/D electrodes, and a gate electrode are disposed on the buffer layer.

A transistor device according to some embodiments includes a channel layer, a barrier layer on the channel layer, and source and drain contacts on the barrier layer, and a gate contact on the barrier layer between the source and drain contacts. The channel layer includes a sub-layer having an increased doping concentration level relative to a remaining portion of the channel layer. The presence of the sub-layer may reduce drain lag without substantially increasing gate lag.