A disclosed transistor structure includes a gate electrode, an active layer, a source electrode, a drain electrode, an insulating layer separating the gate electrode from the active layer, and a carrier modification device that reduces short channel effects by reducing carrier concentration variations in the active layer. The carrier modification device may include a capping layer in contact with the active layer that acts to increase a carrier concentration in the active layer. Alternatively, the carrier modification device may include a first injection layer in contact with the source electrode and the active layer separating the source electrode from the active layer, and a second injection layer in contact with the drain electrode and the active layer separating the drain electrode from the active layer. The first and second injection layers may act to reduce a carrier concentration within the active layer near the source electrode and the drain electrode.

A semiconductor device includes a substrate, a device isolation layer on the substrate, the device isolation layer defining a first active pattern, a pair of first source/drain patterns on the first active pattern, the pair of first source/drain patterns being spaced apart from each other in a first direction, and each of the pair of first source/drain patterns having a maximum first width in the first direction, a first channel pattern between the pair of first source/drain patterns, a gate electrode on the first channel pattern and extends in a second direction intersecting the first direction, and a first amorphous region in the first active pattern, the first amorphous region being below at least one of the pair of first source/drain patterns, and having a maximum second width in the first direction that is less than the maximum first width.

A single crystal semiconductor structure includes: an amorphous substrate; a single crystal semiconductor layer provided on the amorphous substrate; and a thin orienting film provided between the amorphous substrate and the single crystal semiconductor layer, wherein the thin orienting film is a single crystal thin film, and the thin orienting film has a non-zero thickness that is equal to or less than 10 times a critical thickness h.sub.c.

A single crystal semiconductor structure includes: an amorphous substrate; a single crystal semiconductor layer provided on the amorphous substrate; and a thin orienting film provided between the amorphous substrate and the single crystal semiconductor layer, wherein the thin orienting film is a single crystal thin film, and the thin orienting film has a non-zero thickness that is equal to or less than 10 times a critical thickness h.sub.c.

A vertical field effect transistor includes a first epitaxial region in contact with a top surface of a channel fin extending vertically from a bottom source/drain located above a substrate, a second epitaxial region above the first epitaxial region having a horizontal thickness that is larger than a horizontal thickness of the first epitaxial region. The first epitaxial region and the second epitaxial region form a top source/drain region of the semiconductor structure. The first epitaxial region has a first doping concentration and the second epitaxial region has a second doping concentration that is lower than the first doping concentration. A top spacer, adjacent to the first epitaxial region and the second epitaxial region, is in contact with a top surface of a high-k metal gate stack located around the channel fin and in contact with a top surface of a first dielectric layer disposed between adjacent channel fins.

A Schottky diode comprises: a first electrode; a second electrode; and a body of semiconductive material connected to the first electrode at a first interface and connected to the second electrode at a second interface, wherein the first interface comprises a first planar region lying in a first plane and the first electrode has a first projection onto the first plane in a first direction normal to the first plane, the second interface comprises a second planar region lying in a second plane and the second electrode has a second projection onto the first plane in said first direction, at least a portion of the second projection lies outside the first projection, said second planar region is offset from the first planar region in said first direction, and one of the first interface and the second interface provides a Schottky contact.

The present disclosure discloses a FinFET transistor cut etching process method, comprising: step 1, forming a first photoresist pattern to define a cut etching region of the FinFET transistor; step 2, forming a second amorphous semiconductor pattern; step 3, forming a first dielectric layer and a first groove; step 4, forming a second dielectric layer that fully fills the first groove; step 5, performing CMP using the second amorphous semiconductor layer as a stop layer, so as to form a sidewall and a second dielectric layer strip; step 6, performing self-alignment to remove each side wall; step 7, performing a wet process to remove the amorphous semiconductor strip; and step 8: performing etching by using each second dielectric layer strip as a mask, so as to form a fin and achieve cut etching of the FinFET transistor. The present disclosure can enlarge the process window and reduce the process cost.

A semiconductor wafer can include a substrate, a poly template layer, and a semiconductor layer. The substrate has a central region and an edge region, the poly template layer is disposed along a peripheral edge of the substrate, and a semiconductor layer over the central region, wherein the semiconductor layer is monocrystalline. In an embodiment, the poly template layer and the monocrystalline layer are laterally spaced apart from each other by an intermediate region. In another embodiment, the semiconductor layer can include aluminum. A process of forming the substrate can include forming a patterned poly template layer within the edge region and forming a semiconductor layer over the primary surface. Another process of forming the substrate can include forming a semiconductor layer over the primary surface and removing a portion of the semiconductor layer so that the semiconductor layer is spaced apart from an edge of the substrate.

A vertical field effect transistor includes a first epitaxial region in contact with a top surface of a channel fin extending vertically from a bottom source/drain located above a substrate, a second epitaxial region above the first epitaxial region having a horizontal thickness that is larger than a horizontal thickness of the first epitaxial region. The first epitaxial region and the second epitaxial region form a top source/drain region of the semiconductor structure. The first epitaxial region has a first doping concentration and the second epitaxial region has a second doping concentration that is lower than the first doping concentration. A top spacer, adjacent to the first epitaxial region and the second epitaxial region, is in contact with a top surface of a high-k metal gate stack located around the channel fin and in contact with a top surface of a first dielectric layer disposed between adjacent channel fins.

Power is inverted using double-base-contact bidirectional bipolar transistors in a three-level-inverter topology. The transistors not only switch to synthesize a PWM approximation of the desired AC waveform, but also have transient phases of diode conduction before each full turn-on or turn-off.