A semiconductor device includes a substrate including a first main surface; a semiconductor layer provided on the first main surface of the substrate; an electrically insulating layer provided on the semiconductor layer; a source electrode and a drain electrode that are provided on the semiconductor layer; and a gate electrode provided on the electrically insulating layer. The semiconductor layer has an electron transport layer provided on the substrate and including a first upper surface, and has an electron supply layer provided on the electron transport layer. A first opening and a second opening are each formed in the electron supply layer and the electron transport layer. A third opening connected to the first opening and a fourth opening connected to the second opening are each formed in the electrically insulating layer.

A semiconductor device comprises a substrate, one or more first III-semiconductor layers, and a plurality of superlattice structures between the substrate and the one or more first layers. The plurality of superlattice structures comprises an initial superlattice structure and one or more further superlattice structures between the initial superlattice structure and the one or more first layers. The plurality of superlattice structures is configured such that a strain-thickness product of semiconductor layer pairs in each superlattice structure of the one or more further superlattice structures is greater than or equal to a strain-thickness product of semiconductor layer pairs in superlattice structure(s) of the plurality of superlattice structures between that superlattice structure and the substrate. The plurality of superlattice structures is also configured such that a strain-thickness product of semiconductor layer pairs in at least one of the one or more further superlattice structures is greater than a strain-thickness product of semiconductor layer pairs in the initial superlattice structure.

A semiconductor device comprises a substrate, one or more first III-semiconductor layers, and a plurality of superlattice structures between the substrate and the one or more first layers. The plurality of superlattice structures comprises an initial superlattice structure and one or more further superlattice structures between the initial superlattice structure and the one or more first layers. The plurality of superlattice structures is configured such that a strain-thickness product of semiconductor layer pairs in each superlattice structure of the one or more further superlattice structures is greater than or equal to a strain-thickness product of semiconductor layer pairs in superlattice structure(s) of the plurality of superlattice structures between that superlattice structure and the substrate. The plurality of superlattice structures is also configured such that a strain-thickness product of semiconductor layer pairs in at least one of the one or more further superlattice structures is greater than a strain-thickness product of semiconductor layer pairs in the initial superlattice structure.

III-Nitride layers having spatially controlled regions or domains of porosities therein with tunable optical, electrical, and thermal properties are described herein. Also disclosed are methods for preparing and using such III-nitride layers.

A nitride semiconductor device includes a substrate, a first electron transport layer above the substrate, a first electron supply layer above the first electron transport layer, a first nitride semiconductor layer above the first electron supply layer, a first opening passing through the first nitride semiconductor layer and the first electron supply layer and reaching the first electron transport layer, a second electron transport layer disposed above the first nitride semiconductor layer and along the inner surface of the first opening, a second electron supply layer disposed above the second electron transport layer and covering the first opening, a gate electrode disposed above the second electron supply layer and covering the first opening, a source electrode connected to the first nitride semiconductor layer and the second electron transport layer, and a drain electrode.

The invention relates to a lateral field effect transistor, in particular a HEMT having a heterostructure, in a III/V semiconductor system with a p-type semiconductor being arranged between an ohmic load contact, in particular a drain contact, and a gate contact of the transistor for an injection of holes into a portion of the transistor channel. Further, a recombination zone implemented by a floating ohmic contact is provided for to improve the device performance.

The present disclosure provides a semiconductor structure and a manufacturing method therefor. In the semiconductor structure, a semiconductor substrate, a heterojunction and an in-situ insulation layer are disposed from bottom to top, a trench is provided in the in-situ insulation layer, and a transition layer is located on at least an in-situ insulation layer, the p-type semiconductor layer is located in the trench and on the gate region of the transition layer, and the heavily doped n-type layer is located on at least one of the p-type semiconductor layer in the gate region, the source region of the heterojunction, or the drain region of the heterojunction.

A multi-trench super junction IGBT device includes a metallization collector, a P-type substrate, a first N-type epitaxial layer located above the P-type substrate and a second N-type epitaxial layer located above the first N-type epitaxial layer. The second N-type epitaxial layer includes at least a first dummy MOS cell unit and a MOS cell unit, wherein the first dummy MOS cell unit includes a trench formed by reactive ion etching, a thermally grown gate oxide layer provided inside the trench and deposited heavily doped polysilicon located in the gate oxide layer.

We disclose a III-nitride semiconductor based heterojunction power device comprising: a first heterojunction transistor formed on a substrate, the first heterojunction transistor comprising: a first III-nitride semiconductor region formed over the substrate, wherein the first III-nitride semiconductor region comprises a first heterojunction comprising at least one two dimensional carrier gas; a first terminal operatively connected to the first III-nitride semiconductor region; a second terminal laterally spaced from the first terminal and operatively connected to the first III-nitride semiconductor region; a first plurality of highly doped semiconductor regions of a first polarity formed over the first III-nitride semiconductor region, the first plurality of highly doped semiconductor regions being formed between the first terminal and the second terminal; a first gate region operatively connected to the first plurality of highly doped semiconductor regions; and a second heterojunction transistor formed on the substrate. The second heterojunction transistor comprises: a second III-nitride semiconductor region formed over the substrate, wherein the second III-nitride semiconductor region comprises a second heterojunction comprising at least one two dimensional carrier gas; a third terminal operatively connected to the second III-nitride semiconductor region; a fourth terminal laterally spaced from the third terminal in the first dimension and operatively connected to the second III-nitride semiconductor region; a second gate region being formed over the second III-nitride semiconductor region, and between the third terminal and the fourth terminal. One of the first and second heterojunction transistors is an enhancement mode field effect transistor and the other of the first and second heterojunction transistors is a depletion mode field effect transistor.

According to one embodiment, a nitride semiconductor includes a base body, a nitride member, and an intermediate region provided between the base body and the nitride member. The nitride member includes a first nitride region including Al.sub.x1Ga.sub.1-x1N (0<x1≤1), and a second nitride region including Al.sub.x2Ga.sub.1-x2N (0≤x2<1, x2<x1). The first nitride region is between the intermediate region and the second nitride region. The intermediate region includes nitrogen and carbon. A concentration of carbon in the intermediate region is not less than 1.5×10.sup.19/cm.sup.3 and not more than 6×10.sup.20/cm.sup.3.