The invention relates to a lateral field effect transistor, in particular a HEMT having a heterostructure, in a III/V semiconductor system with a p-type semiconductor being arranged between an ohmic load contact, in particular a drain contact, and a gate contact of the transistor for an injection of holes into a portion of the transistor channel. Further, a recombination zone implemented by a floating ohmic contact is provided for to improve the device performance.

The invention relates to a lateral field effect transistor, in particular a HEMT having a heterostructure, in a III/V semiconductor system with a p-type semiconductor being arranged between an ohmic load contact, in particular a drain contact, and a gate contact of the transistor for an injection of holes into a portion of the transistor channel. Further, a recombination zone implemented by a floating ohmic contact is provided for to improve the device performance.

We disclose a III-nitride semiconductor based heterojunction power device comprising: a first heterojunction transistor formed on a substrate, the first heterojunction transistor comprising: a first III-nitride semiconductor region formed over the substrate, wherein the first III-nitride semiconductor region comprises a first heterojunction comprising at least one two dimensional carrier gas; a first terminal operatively connected to the first III-nitride semiconductor region; a second terminal laterally spaced from the first terminal and operatively connected to the first III-nitride semiconductor region; a first plurality of highly doped semiconductor regions of a first polarity formed over the first III-nitride semiconductor region, the first plurality of highly doped semiconductor regions being formed between the first terminal and the second terminal; a first gate region operatively connected to the first plurality of highly doped semiconductor regions; and a second heterojunction transistor formed on the substrate. The second heterojunction transistor comprises: a second III-nitride semiconductor region formed over the substrate, wherein the second III-nitride semiconductor region comprises a second heterojunction comprising at least one two dimensional carrier gas; a third terminal operatively connected to the second III-nitride semiconductor region; a fourth terminal laterally spaced from the third terminal in the first dimension and operatively connected to the second III-nitride semiconductor region; a second gate region being formed over the second III-nitride semiconductor region, and between the third terminal and the fourth terminal. One of the first and second heterojunction transistors is an enhancement mode field effect transistor and the other of the first and second heterojunction transistors is a depletion mode field effect transistor.

We disclose a III-nitride semiconductor based heterojunction power device comprising: a first heterojunction transistor formed on a substrate, the first heterojunction transistor comprising: a first III-nitride semiconductor region formed over the substrate, wherein the first III-nitride semiconductor region comprises a first heterojunction comprising at least one two dimensional carrier gas; a first terminal operatively connected to the first III-nitride semiconductor region; a second terminal laterally spaced from the first terminal and operatively connected to the first III-nitride semiconductor region; a first plurality of highly doped semiconductor regions of a first polarity formed over the first III-nitride semiconductor region, the first plurality of highly doped semiconductor regions being formed between the first terminal and the second terminal; a first gate region operatively connected to the first plurality of highly doped semiconductor regions; and a second heterojunction transistor formed on the substrate. The second heterojunction transistor comprises: a second III-nitride semiconductor region formed over the substrate, wherein the second III-nitride semiconductor region comprises a second heterojunction comprising at least one two dimensional carrier gas; a third terminal operatively connected to the second III-nitride semiconductor region; a fourth terminal laterally spaced from the third terminal in the first dimension and operatively connected to the second III-nitride semiconductor region; a second gate region being formed over the second III-nitride semiconductor region, and between the third terminal and the fourth terminal. One of the first and second heterojunction transistors is an enhancement mode field effect transistor and the other of the first and second heterojunction transistors is a depletion mode field effect transistor.

According to one embodiment, a nitride semiconductor includes a base body, a nitride member, and an intermediate region provided between the base body and the nitride member. The nitride member includes a first nitride region including Al.sub.x1Ga.sub.1-x1N (0<x1≤1), and a second nitride region including Al.sub.x2Ga.sub.1-x2N (0≤x2<1, x2<x1). The first nitride region is between the intermediate region and the second nitride region. The intermediate region includes nitrogen and carbon. A concentration of carbon in the intermediate region is not less than 1.5×10.sup.19/cm.sup.3 and not more than 6×10.sup.20/cm.sup.3.

According to one embodiment, a nitride semiconductor includes a base body, a nitride member, and an intermediate region provided between the base body and the nitride member. The nitride member includes a first nitride region including Al.sub.x1Ga.sub.1-x1N (0<x1≤1), and a second nitride region including Al.sub.x2Ga.sub.1-x2N (0≤x2<1, x2<x1). The first nitride region is between the intermediate region and the second nitride region. The intermediate region includes nitrogen and carbon. A concentration of carbon in the intermediate region is not less than 1.5×10.sup.19/cm.sup.3 and not more than 6×10.sup.20/cm.sup.3.

Provided herein are a wide-bandgap semiconductor bipolar charge trapping (BCT) non-volatile memory structure with only one single insulating layer and a fabrication method thereof. Monolithically integrated enhancement-mode (E-mode) n-channel and p-channel field effect transistors (n-FETs and p-FETs) for gallium nitride (GaN)-based complementary logic (CL) gates based on the proposed memory structure, together with a fabrication method thereof in a single process run and various logic circuits incorporating one or more of the GaN-based CL gates, are also provided herein.

Provided herein are a wide-bandgap semiconductor bipolar charge trapping (BCT) non-volatile memory structure with only one single insulating layer and a fabrication method thereof. Monolithically integrated enhancement-mode (E-mode) n-channel and p-channel field effect transistors (n-FETs and p-FETs) for gallium nitride (GaN)-based complementary logic (CL) gates based on the proposed memory structure, together with a fabrication method thereof in a single process run and various logic circuits incorporating one or more of the GaN-based CL gates, are also provided herein.

According to one embodiment, a nitride semiconductor includes a base body, and a nitride member. The nitride member includes a first nitride region including Al.sub.x1Ga.sub.1-x1N (0<x1≤1), and a second nitride region including Al.sub.x2Ga.sub.1-x2N (0≤x2<1, x2<x1). The first nitride region is between the base body and the second nitride region. The first nitride region includes a first portion and a second portion. The second portion is between the first portion and the second nitride region. An oxygen concentration in the first portion is higher than an oxygen concentration in the second portion. The oxygen concentration in the second portion is not more than 1×10.sup.18/cm.sup.3. A first thickness of the first portion in a first direction from the first to second nitride regions is thinner than a second thickness of the second portion in the first direction.

According to one embodiment, a nitride semiconductor includes a base body, and a nitride member. The nitride member includes a first nitride region including Al.sub.x1Ga.sub.1-x1N (0<x1≤1), and a second nitride region including Al.sub.x2Ga.sub.1-x2N (0≤x2<1, x2<x1). The first nitride region is between the base body and the second nitride region. The first nitride region includes a first portion and a second portion. The second portion is between the first portion and the second nitride region. An oxygen concentration in the first portion is higher than an oxygen concentration in the second portion. The oxygen concentration in the second portion is not more than 1×10.sup.18/cm.sup.3. A first thickness of the first portion in a first direction from the first to second nitride regions is thinner than a second thickness of the second portion in the first direction.