Provided is a cadmium zinc telluride (CdZnTe) single crystal including a main surface that has a high mobility lifetime product (μτ product) in a wide range, wherein the main surface has an area of 100 mm.sup.2 or more and has 50% or more of regions where the μτ product is 1.0×10.sup.−3 cm.sup.2/V or more based on the entire main surface, and a method for effectively producing the same.

Disclosed are a functional photoresist for patterning a nanoparticle thin film including nanoparticles on a substate and a method of patterning a nanoparticle thin film using the functional photoresist, wherein the functional photoresist includes a photoactive compound (PAC); and a functional ligand that is bound to the surfaces of the nanoparticles and controls the physical properties of the nanoparticles.

Embodiments herein describe techniques for an integrated circuit that includes a substrate, a semiconductor device on the substrate, and a contact stack above the substrate and coupled to the semiconductor device. The contact stack includes a contact metal layer, and a semiconducting oxide layer adjacent to the contact metal layer. The semiconducting oxide layer includes a semiconducting oxide material, while the contact metal layer includes a metal with a sufficient Schottky-barrier height to induce an interfacial electric field between the semiconducting oxide layer and the contact metal layer to reject interstitial hydrogen from entering the semiconductor device through the contact stack. Other embodiments may be described and/or claimed.

Passivated semiconductor nanoparticles and methods for the fabrication and use of passivated semiconductor nanoparticles is provided herein.

The present invention discloses an ultra-thin super junction IGBT and a manufacturing method thereof, comprising: a metalized collector; a P-type collector region located on the metalized collector; an N-type FS layer located above the P-type collector region; an N-type FS isolating layer located above the N-type FS layer; a first N-type epitaxial layer located above the N-type FS isolating layer and a second N-type epitaxial layer located above the first N-type epitaxial layer; and a MOS structure located in the second N-type epitaxial layer. According to the present invention, thinning the chip thickness reduces forward conduction voltage drop and switching losses, while reducing thermal resistance and improving current conducting capability.

A method for manufacturing a semiconductor device includes a step of preparing a semiconductor substrate that has a first main surface on one side and a second main surface on the other side, the semiconductor substrate on which a plurality of device forming regions and an intended cutting line that demarcates the plurality of device forming regions are set, a step of forming a first electrode that covers the first main surface in each of the device forming regions, a step of forming a second electrode that covers the second main surface, a step of partially removing the second electrode along the intended cutting line such that the semiconductor substrate is exposed, and forming a removed portion that extends along the intended cutting line, and a step of cutting the semiconductor substrate along the removed portion.

Embodiments of the present disclosure are directed towards an integrated circuit (IC) die. In embodiments, an IC die may include a semiconductor substrate, a group III-Nitride or II-VI wurtzite layer disposed over the semiconductor substrate, and a plurality of buffer structures at least partially embedded in the group III-Nitride or II-VI wurtzite layer. In some embodiments, each of the plurality of buffer structures may include a central member disposed over the semiconductor substrate, a lower lateral member disposed over the semiconductor substrate and extending laterally away from the central member, and an upper lateral member disposed over the central member and extending laterally from the central member in an opposite direction from the lower lateral member. The plurality of buffer structures may be positioned in a staggered arrangement to terminate defects of the group III-Nitride or II-VI wurtzite layer. Other embodiments may be described and/or claimed.

In some aspects, methods of forming a metal sulfide thin film are provided. According to some methods, a metal sulfide thin film is deposited on a substrate in a reaction space in a cyclical process where at least one cycle includes alternately and sequentially contacting the substrate with a first vapor-phase metal reactant and a second vapor-phase sulfur reactant. In some aspects, methods of forming a three-dimensional architecture on a substrate surface are provided. In some embodiments, the method includes forming a metal sulfide thin film on the substrate surface and forming a capping layer over the metal sulfide thin film. The substrate surface may comprise a high-mobility channel.

The present invention provides a semiconductor crystal comprising a semiconductor material having a tuned band gap energy, and methods for preparation thereof. More particularly, the invention provides a semiconductor crystal comprising a semiconductor material and amino acid molecules, peptides, or a combination thereof, incorporated within the crystal lattice, wherein the amino acid molecules, peptides, or combination thereof tune the band gap energy of the semiconductor material.

A process for fabricating a heterostructure made of semiconductor materials having a crystalline structure of wurtzite type, includes the following steps: structuring a surface of a zinc oxide monocrystalline substrate into mesas; depositing by epitaxy at least one layer of semiconductor materials having a crystalline structure of wurtzite type, forming the heterostructure, on top of the structured surface. Heterostructure obtained by such a process. A process for fabricating at least one electronic or optoelectronic device from such a heterostructure is also provided.