A semiconductor laminate includes a silicon carbide substrate having a first main surface and a second main surface opposite the first main surface, and an epitaxial layer composed of silicon carbide disposed on the first main surface. The second main surface has an average value of roughness Ra of 0.1 μm or more and 1 μm or less with a standard deviation of 25% or less of the average value.

A semiconductor laminate includes a silicon carbide substrate having a first main surface and a second main surface opposite the first main surface, and an epitaxial layer composed of silicon carbide disposed on the first main surface. The second main surface has an average value of roughness Ra of 0.1 μm or more and 1 μm or less with a standard deviation of 25% or less of the average value.

A power semiconductor device is disclosed. In one example, the device includes a semiconductor body coupled to a first load terminal structure and a second load terminal structure. An active cell field is implemented in the semiconductor body. The active cell field is surrounded by an edge termination zone. A plurality of first cells and a plurality of second cells are provided in the active cell field. Each first cell includes a first mesa, the first mesa including: a first port region and a first channel region. Each second cell includes a second mesa, the second mesa including a second port region. The active cell field is surrounded by a drainage region that is arranged between the active cell field and the edge termination zone.

According to the present invention, there is provided a SiC epitaxial wafer including: a 4H-SiC single crystal substrate which has a surface with an off angle with respect to a c-plane as a main surface and a bevel part on a peripheral part; and a SiC epitaxial layer having a film thickness of 20 μm or more, which is formed on the 4H-SiC single crystal substrate, in which a density of an interface dislocation extending from an outer peripheral edge of the SiC epitaxial layer is 10 lines/cm or less.

According to the present invention, there is provided a SiC epitaxial wafer including: a 4H-SiC single crystal substrate which has a surface with an off angle with respect to a c-plane as a main surface and a bevel part on a peripheral part; and a SiC epitaxial layer having a film thickness of 20 μm or more, which is formed on the 4H-SiC single crystal substrate, in which a density of an interface dislocation extending from an outer peripheral edge of the SiC epitaxial layer is 10 lines/cm or less.

An SiC semiconductor device includes an SiC semiconductor layer including an SiC monocrystal that is constituted of a hexagonal crystal and having a first main surface as a device surface facing a c-plane of the SiC monocrystal and has an off angle inclined with respect to the c-plane, a second main surface at a side opposite to the first main surface, and a side surface facing an a-plane of the SiC monocrystal and has an angle less than the off angle with respect to a normal to the first main surface when the normal is 0°.

An SiC semiconductor device includes an SiC semiconductor layer including an SiC monocrystal and having a first main surface as an element forming surface, a second main surface at a side opposite to the first main surface, and a plurality of side surfaces connecting the first main surface and the second main surface, and a plurality of modified lines formed one layer each at the respective side surfaces of the SiC semiconductor layer and each extending in a band shape along a tangential direction to the first main surface of the SiC semiconductor layer and modified to be of a property differing from the SiC monocrystal.

A semiconductor structure, including a substrate, a first nitride layer, a polarity inversion layer, a second nitride layer, and a third nitride layer, is provided. The first nitride layer is located on the substrate. The polarity inversion layer is located on a surface of the first nitride layer to convert a non-metallic polarity surface of the first nitride layer into a metallic polarity surface of the polarity inversion layer. The second nitride layer is located on the polarity inversion layer. The third nitride layer is located on the second nitride layer. The substrate, the first nitride layer, the polarity inversion layer, and the second nitride layer include iron element.

A semiconductor structure, including a substrate, a first nitride layer, a polarity inversion layer, a second nitride layer, and a third nitride layer, is provided. The first nitride layer is located on the substrate. The polarity inversion layer is located on a surface of the first nitride layer to convert a non-metallic polarity surface of the first nitride layer into a metallic polarity surface of the polarity inversion layer. The second nitride layer is located on the polarity inversion layer. The third nitride layer is located on the second nitride layer. The substrate, the first nitride layer, the polarity inversion layer, and the second nitride layer include iron element.

A guard ring structure includes a plurality of first groups of concentric guard rings encompassing an active region of an integrated circuit, the concentric guard rings of the first groups having a guard ring pitch of less than 80 nm. The concentric guard rings of the first groups have a single, closed path that is distinct from an adjacent guard ring and defines a rectangular geometry with rounded corners. Second groups of guard rings are interspersed with and concentrically arranged with the first groups, where each corner region of the second groups include at least one guard ring defect. A method of fabricating a guard ring structure for an integrated circuit is also disclosed.