A semiconductor device having a voltage resistant structure in a first aspect of the present invention is provided, comprising a semiconductor substrate, a semiconductor layer on the semiconductor substrate, a front surface electrode above the semiconductor layer, a rear surface electrode below the semiconductor substrate, an extension section provided to a side surface of the semiconductor substrate, and a resistance section electrically connected to the front surface electrode and the rear surface electrode. The extension section may have a lower permittivity than the semiconductor substrate. The resistance section may be provided to at least one of the upper surface and the side surface of the extension section.

A semiconductor device and a process of forming the semiconductor device are disclosed. The semiconductor device type of a high electron mobility transistor (HEMT) has double SiN films on a semiconductor layer, where the first SiN film is formed by the lower pressure chemical vapor deposition (LPCVD) technique, while, the second SiN film is deposited by the plasma assisted CVD (p-CVD) technique. Moreover, the gate electrode has an arrangement of double metals, one of which contains nickel (Ni) as a Schottky metal, while the other is free from Ni and covers the former metal. A feature of the invention is that the first metal is in contact with the semiconductor layer but apart from the second SiN film.

A structure includes a laterally diffused (LD) MOSFET with an n-type drift region disposed on a surface of a substrate and a p-type body region contained in the drift region. The structure further includes an n-type source region contained in the p-type body region; an n-type drain region contained in the n-type drift region; a gate electrode disposed on a gate dielectric overlying a portion of the p-type body region and the n-type drift region and an electrically conductive field shield member disposed within the n-type drift region at least partially beneath the p-type body region and generally parallel to the gate electrode. The electrically conductive buried field shield member is contained within and surrounded by a layer of buried field shield oxide and is common to both a first LD MOSFET and a second LD MOSFET that are connected in parallel. Methods to fabricate the structure are also disclosed.

A high electron mobility transistor (HEMT) includes a buffer layer on a substrate, a barrier layer on the buffer layer, a p-type semiconductor layer on the barrier layer, a first layer adjacent to a first side of the p-type semiconductor layer without extending to a second side of the p-type semiconductor layer, and a second layer adjacent to the second side of the p-type semiconductor layer without extending to the first side of the p-type semiconductor layer.

The structure of a semiconductor device with negative capacitance (NC) dielectric structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure with a fin base portion and a fin top portion on a substrate, forming a spacer structure in a first region of the fin top portion, and forming a gate structure on a second region of the fin top portion. The spacer structure includes a first NC dielectric material and the gate structure includes a gate dielectric layer with a second NC dielectric material different from the first NC dielectric material.

The present invention provides a field effect transistor device and a method for improving the short-channel effect and the output characteristics using the same. The field effect transistor device comprises an active layer comprising a source region, a drain region, and a channel region located between the source region and the drain region; when the device is turned on, an effective channel and an equivalent source and/or equivalent drain away from the effective channel are formed in the channel region, and the field effect transistor device connects the source region with the drain region through the effective channel, and the equivalent source and/or equivalent drain to form an operating current.

The disclosed technology generally relates to a process of forming transistors with high-k dielectric layers, such as selectively high-k dielectric layers. The high-k dielectric layers, which may be used as the gate dielectric, may be selectively grown from two-dimensional semiconductor materials. The process may be adapted for various transistor structures such as planar transistors, three-dimensional transistors, and gate-all-around transistors. Further, the process may also be used to create stacked transistors. In one aspect, a method for manufacturing a semiconductor device includes forming a seed structure over a base layer, forming a two-dimensional (2D) semiconductor layer disposed on the seed structure, and selectively growing a high-k dielectric layer over the 2D semiconductor layer.

The present application teaches, among other innovations, power semiconductor devices in which breakdown initiation regions, on BOTH sides of a die, are located inside the emitter/collector regions, but laterally spaced away from insulated trenches which surround the emitter/collector regions. Preferably this is part of a symmetrically-bidirectional power device of the “B-TRAN” type. In one advantageous group of embodiments (but not all), the breakdown initiation regions are defined by dopant introduction through the bottom of trench portions which lie within the emitter/collector region. In one group of embodiments (but not all), these can advantageously be separated trench portions which are not continuous with the trench(es) surrounding the emitter/collector region(s).

An electronic circuit having a semiconductor device is provided that includes a heterostructure, the heterostructure including a first layer of a compound semiconductor to which a second layer of a compound semiconductor adjoins in order to form a channel for a 2-dimensional electron gas (2DEG), wherein the 2-dimensional electron gas is not present. In aspects, an electronic circuit having a semiconductor device is provided that includes a III-V heterostructure, the III-V heterostructure including a first layer including GaN to which a second layer adjoins in order to form a channel for a 2-dimensional electron gas (2DEG), and having a purity such that the 2-dimensional electron gas is not present. It is therefore advantageous for the present electronic circuit to be enclosed such that, in operation, no light of wavelengths of less than 400 nm may reach the III-V heterostructure and free charge carriers may be generated by these wavelengths.

A lateral transistor tile is formed with first and second collector regions that longitudinally span first and second sides of the transistor tile; and a base region and an emitter region that are between the first and second collector regions and are both centered on a longitudinal midline of the transistor tile. A base-collector current, a collector-emitter current, and a base-emitter current flow horizontally; and the direction of the base-emitter current is perpendicular to the direction of the base-collector current and the collector-emitter current. Lateral BJT transistors having a variety of layouts are formed from a plurality of the tiles and share common components thereof.