The techniques relate to methods and apparatus for sensing an analyte. At least one sensor element is configured to sense an analyte, the at least one sensor element comprising a first portion and a second portion. A first current electrode is attached to the first portion and a second current electrode is attached to the second portion. A first measurement electrode is attached to the first portion and a second measurement electrode is attached to the second portion.

Some embodiments relate to a semiconductor device. The semiconductor device includes a layer disposed over a substrate. A conductive body extends through the layer. A plurality of bar or pillar structures are spaced apart from one another and laterally surround the conductive body. The plurality of bar or pillar structures are generally concentric around the conductive body.

A semiconductor device includes a first transistor in a first region of a substrate and a second transistor in a second region of the substrate. The first transistor includes multiple first semiconductor patterns; a first gate electrode; a first gate dielectric layer; a first source/drain region; and an inner-insulating spacer. The second transistor includes multiple second semiconductor patterns; a second gate electrode; a second gate dielectric layer; and a second source/drain region. The second gate dielectric layer extends between the second gate electrode and the second source/drain region and is in contact with the second source/drain region. The first source/drain region is not in contact with the first gate dielectric layer.

There is provided a solid-state imaging device that includes a photoelectric conversion unit, a transfer gate, a floating diffusion unit, and a transistor. The photoelectric conversion unit produces a charge according to incident light. The transfer gate has a columnar shape having an opening that is continuous in a vertical direction, and transfers the charge from the photoelectric conversion unit. The floating diffusion unit is formed extending to a region surrounded by the opening of the transfer gate, and converts the transferred charge into a voltage signal. The transistor is electrically connected to the floating diffusion unit via a diffusion layer.

A semiconductor device includes a plurality of column portions made of a semiconductor. The plurality of column portions each include a source region, a drain region, and a channel formation region including a channel formed between the source region and the drain region. The semiconductor device further includes: a gate electrode provided at a side wall of the channel formation region with an insulating layer being interposed between the gate electrode and the side wall; a first semiconductor layer coupled to either one of the source region and the drain region of each of the plurality of column portions; and a first metal layer coupled to the first semiconductor layer.

A semiconductor device includes: a semiconductor layer having a partitioned region partitioned by a trench; a field insulating layer which is formed on a main surface of the semiconductor layer at an interval from the trench toward an inner side of the partitioned region and covers the partitioned region; a trench insulating layer formed at least in the trench; an intermediate region annularly formed between the field insulating layer on the main surface of the semiconductor layer and the trench insulating layer; and a bridge insulating layer which is formed in the intermediate region and connects the field insulating layer and the trench insulating layer, wherein the bridge insulating layer has a bridge buried portion buried in the main surface of the semiconductor layer.

A semiconductor device includes: a semiconductor layer having a partitioned region partitioned by a trench; a field insulating layer which is formed on a main surface of the semiconductor layer at an interval from the trench toward an inner side of the partitioned region and covers the partitioned region; a trench insulating layer formed at least in the trench; an intermediate region annularly formed between the field insulating layer on the main surface of the semiconductor layer and the trench insulating layer; and a bridge insulating layer which is formed in the intermediate region and connects the field insulating layer and the trench insulating layer, wherein the bridge insulating layer has a bridge buried portion buried in the main surface of the semiconductor layer.

The present invention introduces a new shielded gate trench MOSFETs wherein epitaxial layer having special multiple stepped epitaxial (MSE) layers with different doping concentrations decreasing in a direction from substrate to body regions, wherein each of the MSE layers has uniform doping concentration as grown. Specific on-resistance is significantly reduced with the special MSE structure. Moreover, in sore preferred embodiment, an MSO (multiple stepped oxide) structure is applied to the shielded gate structure to further reduce the specific on-resistance and enhance device ruggedness.

Provided is a semiconductor device including: a drift region of first conductivity type provided in a semiconductor substrate; a base region of second conductivity type provided in the semiconductor substrate; an emitter region of first conductivity type provided at a front surface of the semiconductor substrate; a contact region of second conductivity type provided on the base region and having a higher doping concentration than the base region; a contact trench portion provided at the front surface of the semiconductor substrate; a first barrier layer provided at a side wall and a bottom surface of the contact trench portion; and a second barrier layer provided in contact with the contact region at the side wall of the contact trench portion.

Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate. Each of the nanowires includes a discrete channel region disposed in the nanowire. A gate electrode stack surrounds the plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is disposed on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires.