Disclosed is a method for manufacturing a semiconductor device. The method includes: forming a gate insulating material layer on a substrate; forming a gate material layer on the gate insulating material layer; and performing an etching process on the gate material layer and the gate insulating material layer to form a gate layer and a gate insulating layer. The gate insulating layer and the gate layer each include a first end and a second end opposite to each other in a direction parallel to a channel length. The first end of the gate insulating layer is recessed inwards by a preset length relative to the first end of the gate layer, and the second end of the gate insulating layer is recessed inwards by the preset length relative to the second end of the gate layer.

A method of producing a power semiconductor device includes: providing a semiconductor body; forming, at the semiconductor body, a polycrystalline semiconductor region; forming, at the polycrystalline semiconductor region, an amorphous sublayer; subjecting the amorphous sublayer to a re-crystallization processing step to form a re-crystallized sublayer; and forming a metal layer at the re-crystallized sublayer.

A method of manufacturing a semiconductor structure and a semiconductor structure are disclosed. The method of manufacturing a semiconductor structure includes: providing a substrate; forming multiple support structures on the substrate, where the multiple support structures are arranged at intervals along a first direction, and a gate trench is formed between every two adjacent support structures; forming a gate structure in the gate trench; and removing a part of each of the support structures, such that each of retained support structures forms two isolation sidewalls spaced apart, the two isolation sidewalls are arranged on opposite sidewalls of the adjacent gate structures respectively, and a filling region is formed by the two isolation sidewalls.

A semiconductor structure includes at least two field effect transistors. A gate strip including a plurality of gate dielectrics and a gate electrode strip can be formed over a plurality of semiconductor active regions. Source/drain implantation is conducted using the gate strip as a mask. The gate strip is divided into gate electrodes after the implantation.

An embodiment of a method of integration of a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming a pad dielectric layer of a MOS device above a first region of a substrate; forming a channel of the memory device from a thin film of semiconducting material overlying a surface above a second region of the substrate, the channel connecting a source and drain of the memory device; forming a patterned dielectric stack overlying the channel above the second region, the patterned dielectric stack comprising a tunnel layer, a charge-trapping layer, and a sacrificial top layer; simultaneously removing the sacrificial top layer from the second region of the substrate, and the pad dielectric layer from the first region of the substrate; and simultaneously forming a gate dielectric layer above the first region of the substrate and a blocking dielectric layer above the charge-trapping layer.

A semiconductor structure includes a metal gate structure comprising a gate dielectric layer and a gate electrode, a conductive layer disposed over the metal gate structure, and a contact feature in direct contact with the top portion of the conductive layer, where the conductive layer includes a bottom portion disposed below a top surface of the metal gate structure and a top portion disposed over the top surface of the metal gate structure, and where the top portion laterally extends beyond a sidewall of the bottom portion.

The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure, and relates to the technical field of semiconductors. The manufacturing method includes: providing a base, wherein the base is provided with an active region; forming a gate layer on the base; forming isolation structures on a periphery of the gate layer, wherein in a direction away from the gate layer, each of the isolation structures at least includes a hollow portion and an isolation portion; forming an insulating structure on top surfaces of the isolation structures; forming contact plugs, wherein the contact plugs penetrate the insulating structure; an end of each of the contact plugs close to the base is electrically connected to the active region; each of the contact plugs is located on a side of each of the isolation structures away from the gate layer.

A semiconductor device including a barrier layer surrounding a work function metal layer and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate; a first channel region over the semiconductor substrate; a second channel region over the first channel region; gate dielectric layers surrounding the first channel region and the second channel region; work function metal layers surrounding the gate dielectric layers; and barrier layers surrounding the work function metal layers, a first barrier layer surrounding the first channel region being merged with a second barrier layer surrounding the second channel region.

A semiconductor device includes a substrate having a conductive region and an insulating region; gate electrodes including sub-gate electrodes spaced apart from each other and stacked in a first direction perpendicular to an upper surface of the substrate and extending in a second direction perpendicular to the first direction and gate connectors connecting the sub-gate electrodes disposed on the same level; channel structures penetrating through the gate electrodes and extending in the conductive region of the substrate; and a first dummy channel structure penetrating through the gate electrodes and extending in the insulating region of the substrate and disposed adjacent to at least one side of the gate connectors in a third direction perpendicular to the first and second directions.

A method for forming a semiconductor device includes forming a metal gate stack having a gate dielectric layer and a gate electrode disposed over the gate dielectric layer. The gate electrode includes a first metal layer and a second metal layer. The method further includes performing a plasma treatment to a top surface of the metal gate stack and forming a conductive layer over the treated top surface of the metal gate stack. A top portion of the conductive layer is formed above a top surface of the gate dielectric layer, and a bottom portion of the conductive layer penetrates into the first and the second metal layers of the gate electrode at different distances.