A method of manufacturing an integrated circuit device including a self-aligned air spacer including the operations of forming a dummy gate, forming a sidewall on the dummy gate, forming a dummy layer on the sidewall, constructing a gate structure within an opening defined by the sidewall, removing at least a portion of the first dummy layer to form a first recess between the sidewall layer and the dummy gate, and capping the first recess to form a first air spacer.

Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and include second regions proximate to the control gate regions. High-k dielectric structures are directly against the control gate regions and extend entirely across the insulative levels. Charge-blocking material is adjacent to the high-k dielectric structures. Charge-storage material is adjacent to the charge-blocking material. The charge-storage material is configured as segments which are vertically stacked one atop another, and which are vertically spaced from one another. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies, and methods of forming integrated assemblies.

Processing methods may be performed to form an airgap in a semiconductor structure. The methods may include forming a high-k material on a floor of a trench. The trench may be defined on a semiconductor substrate between sidewalls of a first material and a spacer material. The methods may include forming a gate structure on the high-k material. The gate structure may contact the first material along each sidewall of the trench. The methods may also include etching the first material. The etching may form an airgap adjacent the gate structure.

A semiconductor device with air spacers and air caps and a method of fabricating the same are disclosed. The semiconductor device includes a substrate and a fin structure disposed on the substrate. The fin structure includes a first fin portion and a second fin portion. The semiconductor device further includes a source/drain (S/D) region disposed on the first fin portion, a contact structure disposed on the S/D region, a gate structure disposed on the second fin portion, an air spacer disposed between a sidewall of the gate structure and the contact structure, a cap seal disposed on the gate structure, and an air cap disposed between a top surface of the gate structure and the cap seal.

A semiconductor device and a method of forming the same are provided. The method includes forming a sacrificial gate structure over an active region. A first spacer layer is formed along sidewalls and a top surface of the sacrificial gate structure. A first protection layer is formed over the first spacer layer. A second spacer layer is formed over the first protection layer. A third spacer layer is formed over the second spacer layer. The sacrificial gate structure is replaced with a replacement gate structure. The second spacer layer is removed to form an air gap between the first protection layer and the third spacer layer.

Provided are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic apparatus including the semiconductor device. According to the embodiments, the semiconductor device may include: a vertical structure extending in a vertical direction relative to a substrate; and a nanosheet extending from the vertical structure and spaced apart from the substrate in the vertical direction, wherein the nanosheet includes a first portion in a first orientation, and at least one of an upper surface and a lower surface of the first portion is not parallel to a horizontal surface of the substrate.

A semiconductor device and a method of forming the same are provided. In an embodiment, an exemplary semiconductor device includes a vertical stack of channel members disposed over a substrate, a gate structure wrapping around each channel member of the vertical stack of channel members, and a source/drain feature disposed over the substrate and coupled to the vertical stack of channel members. The source/drain feature is spaced apart from a sidewall of the gate structure by an air gap and a dielectric layer, and the air gap extends into the source/drain feature.

A semiconductor structure and a method for preparing a semiconductor structure are provided. The method for preparing the semiconductor structure includes operations as follows. A substrate is provided, and a plurality of gate structures are arranged at intervals on the substrate. A sacrificial sidewall with a preset thickness is formed on a sidewall of the gate structure. A first dielectric layer is formed between adjacent sacrificial sidewalls, a top of the first dielectric layer being flush with a top of the gate structure and a top of the sacrificial sidewalls. The sacrificial sidewall is removed and an air gap structure is formed on the sidewall of the gate structure. A second dielectric layer is formed, the second dielectric layer covering the top of the gate structure, a top opening of the air gap structure and the top of the first dielectric layer.

A method of forming a semiconductor device that includes forming a trench adjacent to a gate structure to expose a contact surface of one of a source region and a drain region. A sacrificial spacer may be formed on a sidewall of the trench and on a sidewall of the gate structure. A metal contact may then be formed in the trench to at least one of the source region and the drain region. The metal contact has a base width that is less than an upper surface width of the metal contact. The sacrificial spacer may be removed, and a substantially conformal dielectric material layer can be formed on sidewalls of the metal contact and the gate structure. Portions of the conformally dielectric material layer contact one another at a pinch off region to form an air gap between the metal contact and the gate structure.

A semiconductor device includes an active pattern on a substrate, a source/drain pattern on the active pattern, a channel pattern connected to the source/drain pattern, the channel pattern including semiconductor patterns stacked and spaced apart from each other, a gate electrode extending across the channel pattern, and inner spacers between the gate electrode and the source/drain pattern. The semiconductor patterns include stacked first and second semiconductor patterns. The gate electrode includes first and second portions, which are sequentially stacked between the substrate and the first and second semiconductor patterns, respectively. The inner spacers include first and second air gaps, between the first and second portions of the gate electrode and the source/drain pattern. The largest width of the first air gap is larger than that of the second air gap.