A vertical field-effect transistor (VFET) includes: a fin structure on a substrate; a gate structure including a gate dielectric layer on an upper portion of a sidewall of the fin structure, and a conductor layer on a lower portion of the gate dielectric layer; a top source/drain (S/D) region above the fin structure and the gate structure; a bottom S/D region below the fin structure and the gate structure; a top spacer on an upper portion of the gate dielectric layer, and between the top S/D region and a top surface of the conductor layer; and a bottom spacer between the gate structure and the bottom S/D region. A top surface of the gate dielectric layer is positioned at the same or substantially same height as or positioned lower than a top surface of the top spacer, and higher than the top surface of the conductor layer.

A method of manufacturing a silicon carbide semiconductor device includes formation of an electrode and formation of a gate wiring. The electrode is formed to be electrically connected to a base layer and an impurity region included in a semiconductor substrate through a first contact hole. The gate wiring is formed to be electrically connected to a connection wiring through a second contact hole, and is made of material capable of deoxidizing an oxide film. The oxide film is removed by deoxidizing the oxide film formed on the connection wiring to remove the oxygen from the oxide film into the gate wiring through heating treatment for the gate wiring in the formation of the gate wiring or after the formation of the gate wiring.

Two or more types of fin-based transistors having different gate structures and formed on a single integrated circuit are described. The gate structures for each type of transistor are distinguished at least by the thickness or composition of the gate dielectric layer(s) or the composition of the work function metal layer(s) in the gate electrode. Methods are also provided for fabricating an integrated circuit having at least two different types of fin-based transistors, where the transistor types are distinguished by the thickness and composition of the gate dielectric layer(s) and/or the thickness and composition of the work function metal in the gate electrode.

In a method of forming a FinFET, a first sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is recessed so that a remaining layer of the first sacrificial layer is formed on the isolation insulating layer and an upper portion of the source/drain structure is exposed. A second sacrificial layer is formed on the remaining layer and the exposed source/drain structure. The second sacrificial layer and the remaining layer are patterned, thereby forming an opening. A dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned first and second sacrificial layers are removed to form a contact opening over the source/drain structure. A conductive layer is formed in the contact opening.

The structure of a semiconductor device with passivation layers on active regions of FET devices and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions disposed on the substrate, nanostructured channel regions disposed between the first and second S/D regions, a passivation layer, and a nanosheet (NS) structure wrapped around the nanostructured channel regions. Each of the S/D regions have a stack of first and second semiconductor layers arranged in an alternating configuration and an epitaxial region disposed on the stack of first and second semiconductor layers. A first portion of the passivation layer is disposed between the epitaxial region and the stack of first and second semiconductor layers and a second portion of the passivation layer is disposed on sidewalls of the nanostructured channel regions.

According to one embodiment, a semiconductor device includes first to third electrodes, a semiconductor member, and a first insulating member. The third electrode is between the first and second electrodes. The semiconductor member includes first and second semiconductor regions. The first semiconductor region includes first to fifth partial regions. The fourth partial region is between the first and third partial regions. The fifth partial region is between the third and second partial regions. The second semiconductor region includes first and second semiconductor portions. The first insulating member includes first to third insulating regions. The fourth partial region includes a first facing region. The fifth partial region includes a second facing region. The first facing region includes a first element. The second facing region does not include the first element, or a concentration of the first element in the second facing region is lower than in the first facing region.

Embodiments described herein may be related to apparatuses, processes, and techniques related to protecting metal gates within transistor gate structures during SAC patterning. In particular, embodiments include area selective deposition techniques to deposit films on the gate or on a gate cap that have a good selectivity to SAC etch. In embodiments the film may include a combination of zirconium and/or oxygen, or may include zirconium oxide. Other embodiments may be described and/or claimed.

A semiconductor structure includes: a channel layer; an active layer over the channel layer, wherein the active layer is configured to form a two-dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer; a gate electrode over a top surface of the active layer; and a source/drain electrode over the top surface of the active layer; wherein the active layer includes a first layer and a second layer sequentially disposed therein from the top surface to a bottom surface of the active layer, and the first layer possesses a higher aluminum (Al) atom concentration compared to the second layer. An HEMT structure and an associated method are also disclosed.

A non-volatile memory device includes a substrate. A plurality of shallow trench isolation (STI) lines are disposed on the substrate and extend along a first direction. A memory gate structure is disposed on the substrate between adjacent two of the plurality of STI lines. A trench line is disposed in the substrate and extends along a second direction intersecting the first direction, wherein the trench line also crosses top portions of the plurality of STI lines. A conductive line is disposed in the trench line and used as a selection line to be coupled to the memory gate structure.

The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a first active region and a second fin active region extruded from a semiconductor substrate; an isolation featured formed in the semiconductor substrate and being interposed between the first and second fin active regions; a dielectric gate disposed on the isolation feature; a first gate stack disposed on the first fin active region and a second gate stack disposed on the second fin active region; a first source/drain feature formed in the first fin active region and interposed between the first gate stack and the dielectric gate; a second source/drain feature formed in the second fin active region and interposed between the second gate stack and the dielectric gate; a contact feature formed in a first inter-level dielectric material layer and landing on the first and second source/drain features and extending over the dielectric gate.