Some embodiments include an integrated assembly having a first graphene-containing-material offset from a second graphene-containing-material. The first graphene-containing-material includes a first graphene-layer-stack with first metal interspersed therein. The second graphene-containing-material includes a second graphene-layer-stack with second metal interspersed therein. A conductive interconnect couples the first and second graphene-containing materials to one another.

A doped diamond semiconductor and method of production using a laser is disclosed herein. As disclosed, a dopant and/or a diamond or sapphire seed material may be added to a graphite based ablative layer positioned below a confinement layer, the ablative layer also being graphite based and positioned above a backing layer, to promote formation of diamond particles having desirable semiconductor properties via the action of a laser beam upon the ablative layer. Dopants may be incorporated into the process to activate the reaction sought to produce a material useful in production of a doped semiconductor or a doped conductor suitable for the purpose of modulating the electrical, thermal or quantum properties of the material produced. As disclosed, the diamond particles formed by either the machine or method of confined pulsed laser deposition disclosed may be arranged as semiconductors, electrical components, thermal components, quantum components and/or integrated circuits.

Some embodiments include an integrated assembly having a first graphene-containing-material offset from a second graphene-containing-material. The first graphene-containing-material includes a first graphene-layer-stack with first metal interspersed therein. The second graphene-containing-material includes a second graphene-layer-stack with second metal interspersed therein. A conductive interconnect couples the first and second graphene-containing materials to one another.

A doped diamond semiconductor and method of production using a laser is disclosed herein. As disclosed, a dopant and/or a diamond or sapphire seed material may be added to a graphite based ablative layer positioned below a confinement layer, the ablative layer also being graphite based and positioned above a backing layer, to promote formation of diamond particles having desirable semiconductor properties via the action of a laser beam upon the ablative layer. Dopants may be incorporated into the process to activate the reaction sought to produce a material useful in production of a doped semiconductor or a doped conductor suitable for the purpose of modulating the electrical, thermal or quantum properties of the material produced. As disclosed, the diamond particles formed by either the machine or method of confined pulsed laser deposition disclosed may be arranged as semiconductors, electrical components, thermal components, quantum components and/or integrated circuits.

A buffer layer is employed to fabricate diamond membranes and allow reuse of diamond substrates. In this approach, diamond membranes are fabricated on the buffer layer, which in turn is disposed on a diamond substrate that is lattice-matched to the diamond membrane. The weak bonding between the buffer layer and the diamond substrate allows ready release of the fabricated diamond membrane. The released diamond membrane is transferred to another substrate to fabricate diamond devices, while the diamond substrate is reused for another fabrication.

A thin film transistor and a producing method thereof, and an array substrate, which belong to a technical field of the thin film transistor, can solve a problem of poor performance of a conventional thin film transistor. The producing method of the thin film transistor comprises: S1: forming a gate electrode (11) composed of graphene; S2: forming a gate insulating layer (12) composed of oxidized graphene; S3: forming an active region (13) composed of doped oxidized graphene or doped graphene; S4: forming a source electrode (14) and a drain electrode (15) composed of graphene, wherein, the graphene composing the source electrode (14), the drain electrode (15) and the gate electrode (11) is formed by reducing oxidized graphene, and the doped oxidized graphene or doped graphene composing the active region (13) is formed by treating oxidized graphene.

A nanomaterial ribbon patterning method includes: forming a first nanomaterial layer having a first threshold strain on an upper surface of a substrate; forming a second nanomaterial layer on an upper surface of the first nanomaterial layer; forming a thin layer having a second threshold strain smaller than the first threshold strain on an upper surface of the second nanomaterial layer; generating plural cracks on the thin layer and the second nanomaterial layer by applying tensile force to the substrate; placing a mask on an upper surface of the thin layer; removing the mask and peeling off the sacrificial layer on the upper surface of the thin layer; and removing the sacrificial layer to form a nanomaterial ribbon pattern.

A graphene wiring structure of an embodiment has a multilayered graphene having a plurality of planar graphene sheets laminated, and a first interlayer substance being a metal oxyhalide between the plurality of planar graphene sheets.

Various graphene-based photodetectors are disclosed. An example photodetector device may include: a substrate; a first antenna component fabricated on the substrate, the first antenna component comprising one or more antenna electrodes; a second antenna component fabricated on the substrate, the second antenna component comprising one or more antenna electrodes; a source region coupled to the first antenna component and the substrate; and a drain region coupled to the second antenna component and the substrate; wherein the one or more antenna electrodes in the first antenna component and the second antenna component are made of graphene.

Systems, apparatuses, and methods relating to memory devices and packaging are described. A device, such as a dual inline memory module (DIMM) or other electronic device package, may include a substrate with a layer of graphene configured to conduct thermal energy (e.g., heat) away from components mounted or affixed to the substrate. In some examples, a DIMM includes an uppermost or top layer of graphene that is exposed to the air and configured to allow connection of memory devices (e.g., DRAMs) to be soldered to the conducting pads of the substrate. The graphene may be in contact with parts of the memory device other than the electrical connections with the conducting pads and may thus be configured as a heat sink for the device. Other thin, conductive layers of may be used in addition to or as an alternative to graphene. Graphene may be complementary to other heat sink mechanisms.