Some embodiments include an integrated assembly having a first graphene-containing-material offset from a second graphene-containing-material. The first graphene-containing-material includes a first graphene-layer-stack with first metal interspersed therein. The second graphene-containing-material includes a second graphene-layer-stack with second metal interspersed therein. A conductive interconnect couples the first and second graphene-containing materials to one another.

Systems, apparatuses, and methods relating to memory devices and packaging are described. A device, such as a dual inline memory module (DIMM) or other electronic device package, may include a substrate with a layer of graphene configured to conduct thermal energy (e.g., heat) away from components mounted or affixed to the substrate. In some examples, a DIMM includes an uppermost or top layer of graphene that is exposed to the air and configured to allow connection of memory devices (e.g., DRAMs) to be soldered to the conducting pads of the substrate. The graphene may be in contact with parts of the memory device other than the electrical connections with the conducting pads and may thus be configured as a heat sink for the device. Other thin, conductive layers of may be used in addition to or as an alternative to graphene. Graphene may be complementary to other heat sink mechanisms.

A Field Effect Transistor (FET) device and a method for manufacturing it are disclosed. The FET device contains a graphene layer, a composite gate dielectric layer disposed above the graphene layer, wherein the composite gate layer is passivated with fluorine, and a metal gate disposed above the composite gate dielectric layer. The method disclosed teaches how to manufacture the FET device.

A semiconductor device and method of formation are provided. The semiconductor device includes a substrate, a first active area over the substrate, a second active area over the substrate, a graphene channel between the first active area and the second active area, and a first in-plane gate. In some embodiments, the graphene channel, the first in-plane gate, the first active area, and the second active area include graphene. A method of forming the first in-plane gate, the first active area, the second active area, and the graphene channel from a single layer of graphene is also provided.

Provided are a graphene preparation apparatus, including: a chamber having a space for preparation of graphene; a first electrode and a second electrode disposed in the chamber to be separated a predetermined distance from each other, the first electrode and the second electrode supporting a catalytic metal and receiving electric current for preparation of the graphene to heat the catalytic metal using Joule heating; additional heaters disposed at opposite sides of the catalytic metal, respectively, and heating the catalytic metal to compensate for a temperature difference between both end regions and a central region of the catalytic metal heated using Joule heating induced by the first electrode and the second electrode; and a current supply unit supplying electric current to the first electrode and the second electrode.

Various graphene-based photodetectors are disclosed. An example photodetector device may include: a substrate; a first antenna component fabricated on the substrate, the first antenna component comprising one or more antenna electrodes; a second antenna component fabricated on the substrate, the second antenna component comprising one or more antenna electrodes; a source region coupled to the first antenna component and the substrate; and a drain region coupled to the second antenna component and the substrate; wherein the one or more antenna electrodes in the first antenna component and the second antenna component are made of graphene.

Systems, apparatuses, and methods relating to memory devices and packaging are described. A device, such as a dual inline memory module (DIMM) or other electronic device package, may include a substrate with a layer of graphene configured to conduct thermal energy (e.g., heat) away from components mounted or affixed to the substrate. In some examples, a DIMM includes an uppermost or top layer of graphene that is exposed to the air and configured to allow connection of memory devices (e.g., DRAMs) to be soldered to the conducting pads of the substrate. The graphene may be in contact with parts of the memory device other than the electrical connections with the conducting pads and may thus be configured as a heat sink for the device. Other thin, conductive layers of may be used in addition to or as an alternative to graphene. Graphene may be complementary to other heat sink mechanisms.

Provided are a method for manufacturing an electronic device capable of efficiently utilizing a material and a method for removing impurities using the same. The method for manufacturing an electronic device comprises the steps of: placing a transfer film on a plurality of functional layers which are positioned apart from each other on a source substrate; bringing a first transfer target into close contact with the lower surface of the transfer film by applying pressure to a portion of the transfer film that corresponds to the first transfer target from among the plurality of functional layers by using a probe; separating the transfer film from the source substrate in a state in which the first transfer target is in close contact with the lower surface; placing the transfer film on a target substrate in the state in which the first transfer target is in close contact with the lower surface; placing the first transfer target on the target substrate by applying pressure to a portion of the transfer film that corresponds to the first transfer target; and separating the transfer film from the target substrate in a state in which the first transfer target is positioned on the target surface.

A method of forming a vertical metal-air transistor device is provided. The method includes forming a precursor stack with a stack template on the precursor stack on a substrate. The method further includes forming a bottom spacer on the substrate around the precursor stack, and depositing a liner casing on the precursor stack. The method further includes depositing a conductive gate layer on the bottom spacer and liner casing. The method further includes reducing the size of the stack template to form a template post on the precursor stack, and forming a stack cap on the template post and precursor stack.

Disclosed is a nanofilm, a thin film transistor and manufacture methods thereof. The nanofilm of the present disclosure comprises a plurality of regions distributed in a film plane dimension, wherein each of the regions is composed of one kind of nanomaterial, and nanomaterials of adjacent regions are different from each other and contact with each other to form a heterojunction or a Schottky junction.