Provided are electronic devices and methods of manufacturing the same. An electronic device may include a substrate, a gate electrode on the substrate, a ferroelectric layer between the substrate and the gate electrode, and a carbon layer between the substrate and the ferroelectric layer. The carbon layer may have an sp.sup.2 bonding structure.

Provided are electronic devices and methods of manufacturing the same. An electronic device may include a substrate, a gate electrode on the substrate, a ferroelectric layer between the substrate and the gate electrode, and a carbon layer between the substrate and the ferroelectric layer. The carbon layer may have an sp.sup.2 bonding structure.

According to some embodiments, a method for stabilizing electrical properties of a diamond semiconductor comprises terminating a surface of a diamond with hydrogen (H) or deuterium (D) atoms and over-coating the surface of the diamond with an encapsulating material comprising metal oxide salt doped with one or more elements capable of generating negative charge in the metal oxide salt.

An integrated circuit (IC) device may include a semiconductor structure. The semiconductor structure may include a source contact, a drain contact, and a gate. A first fluorocarbon spacer may be between the gate and the source contact. A second fluorocarbon spacer may be between the gate and the drain contact.

A voltage tunable solar-blind UV detector using a EG/SiC heterojunction based Schottky emitter bipolar phototransistor with EG grown on p-SiC epi-layer using a chemically accelerated selective etching process of Si using TFS precursor.

Techniques for integrating a self-aligned heterojunction for TFETs in a vertical GAA architecture are provided. In one aspect, a method of forming a vertical TFET device includes: forming a doped SiGe layer on a Si substrate; forming fins that extend through the doped SiGe layer and partway into the Si substrate such that each of the fins includes a doped SiGe portion disposed on a Si portion with a heterojunction therebetween, wherein the SiGe portion is a source and the Si portion is a channel; selectively forming oxide spacers, aligned with the heterojunction, along opposite sidewalls of only the doped SiGe portion; and forming a gate stack around the Si portion and doped SiGe that is self-aligned with the heterojunction. A vertical TFET device formed by the method is also provided.

Provided are a graphene-based laminate, a method of preparing the same, and a transparent electrode and an electronic device each including the graphene-based laminate. The graphene-based laminate includes a substrate, a graphene layer including graphene and disposed on at least one surface of the substrate, and a metal oxide layer disposed on at least one surface of the graphene layer, wherein the metal oxide layer includes a metal oxide having a greater work function than that of the graphene, and the metal oxide layer includes the metal oxide in an amount of 1 g to 1 mg per unit area of 1 cm.sup.2 of the graphene layer.

The methods of gate extraction and injection FET and channel carrier quantity control related to microelectronics technology and semiconductor technology. The gate extraction and injection FET of the invention is provided with a source, a drain, a gate and a channel semiconductor area on the insulating layer. A gate dielectric layer is arranged between the gate and the channel semiconductor region, wherein, the gate dielectric layer is a thin film material with resistance values of 10.sup.3-10.sup.16 and the channel semiconductor region is a two-dimensional semiconductor or a three-dimensional semiconductor with two-dimensional semiconductor material characteristics (1-10 cellular crystal layers). The advantages of the invention are that the power consumptions of the devices and the integrated circuits can be greatly reduced by a few orders of magnitude.

A field effect transistor and a manufacturing method thereof are provided. The field effect transistor includes two top gate structures (1031C and 1031D) and two bottom gate structures (1032A and 1032B). The top gate structures (1031C and 1031D) and the bottom gate structures (1032A and 1032B) are opposite to each other in pair. This increases a quantity of control-voltage-induced carriers in the field effect transistor, and therefore increases an output current of the field effect transistor, improves a power gain limit frequency in high-frequency use, and makes an electric field between the top gate structures (1031C and 1031D) and the bottom gate structures (1032A and 1032B) more adequately cover a channel layer (106) between source structures (1041 and 1042) and a drain (105), thereby reducing a parasitic effect in a high frequency, and further improving a frequency characteristic of the field effect transistor.

Provided are electronic devices and methods of manufacturing the same. An electronic device may include a substrate, a gate electrode on the substrate, a ferroelectric layer between the substrate and the gate electrode, and a carbon layer between the substrate and the ferroelectric layer. The carbon layer may have an sp.sup.2 bonding structure.