Provided are electronic devices and methods of manufacturing the same. An electronic device may include a substrate, a gate electrode on the substrate, a ferroelectric layer between the substrate and the gate electrode, and a carbon layer between the substrate and the ferroelectric layer. The carbon layer may have an sp.sup.2 bonding structure.

A method can be used for manufacturing a metal substrate structure for a semiconductor power module. A plurality of terminals are welded to a metal top layer. After the welding, a dielectric layer is coupled between the metal top layer and a metal bottom layer. The dielectric can be laminated or molded, as examples.

Provided are electronic devices and methods of manufacturing the same. An electronic device may include a substrate, a gate electrode on the substrate, a ferroelectric layer between the substrate and the gate electrode, and a carbon layer between the substrate and the ferroelectric layer. The carbon layer may have an sp.sup.2 bonding structure.

Provided is a semiconductor device according to an embodiment including an i-type or first-conductivity-type first diamond semiconductor layer having a first side surface, a second-conductivity-type second diamond semiconductor layer provided on the first diamond semiconductor layer and having a second side surface, a third diamond semiconductor layer being in contact with the first side surface and the second side surface, the third diamond semiconductor containing nitrogen, a first electrode electrically connected to the first diamond semiconductor layer, and a second electrode electrically connected to the second diamond semiconductor layer.

A graphene transistor includes an insulating film extending in a first direction and a second direction, the second direction crossing the first direction; graphene located on the insulating film, the graphene including a first opening and a second opening separated from each other in the first direction; a first electrode, the first electrode contacting an upper surface of the graphene, contacting an edge of the graphene positioned in the first opening, and contacting the insulating film in the first opening; and a second electrode, the second electrode contacting the upper surface of the graphene, contacting an edge of the graphene positioned in the second opening, and contacting the insulating film in the second opening.

A voltage tunable solar-blind UV detector using a EG/SiC heterojunction based Schottky emitter bipolar phototransistor with EG grown on p-SiC epi-layer using a chemically accelerated selective etching process of Si using TFS precursor.

An electronic device includes a two-dimensional electron system (2DES) having a two-dimensional electron gas (2DEG) area, and a plurality of contacts arranged around the 2DEG area. Charge particle transport is confined within the 2DEG area and the charge particle transport within the 2DEG area operates within ballistic or hydrodynamic transport regimes. Examples of the two-dimensional system include free-standing graphene, heterostructures of GaAs/2DEG/AlGaAs and hBN/graphene/hBN, among others. Embodiments of the two-dimensional electronic devices include amplifiers, electronic vortex switches, frequency mixers, rectifiers, multipliers, electrically-controlled micro-scale magnetic field generators, sensors, magnetic sensors, bolometers, and phase shifters, among others.

A voltage tunable solar-blind UV detector using a EG/SiC heterojunction based Schottky emitter bipolar phototransistor with EG grown on p-SiC epi-layer using a chemically accelerated selective etching process of Si using TFS precursor.

According to some embodiments, a method for stabilizing electrical properties of a diamond semiconductor comprises terminating a surface of a diamond with hydrogen (H) or deuterium (D) atoms and over-coating the surface of the diamond with an encapsulating material comprising metal oxide salt doped with one or more elements capable of generating negative charge in the metal oxide salt.

The methods of gate extraction and injection FET and channel carrier quantity control related to microelectronics technology and semiconductor technology. The gate extraction and injection FET of the invention is provided with a source, a drain, a gate and a channel semiconductor area on the insulating layer. A gate dielectric layer is arranged between the gate and the channel semiconductor region, wherein, the gate dielectric layer is a thin film material with resistance values of 10.sup.3-10.sup.16Ω and the channel semiconductor region is a two-dimensional semiconductor or a three-dimensional semiconductor with two-dimensional semiconductor material characteristics (1-10 cellular crystal layers). The advantages of the invention are that the power consumptions of the devices and the integrated circuits can be greatly reduced by a few orders of magnitude.