Disclosed is a circuit arrangement. The circuit arrangement includes: an electronic circuit integrated in a semiconductor body; an input pin coupled to the electronic circuit; an insulation layer formed on top of the semiconductor body; and a protection device connected to the input pin. The protection device is integrated in a polysilicon layer formed on top of the insulation layer.

A semiconductor device including an interconnect. The interconnect is arranged to transfer current from one terminal to another, and the interconnect includes a first layer including a plurality of interweaved fingers, and each of the interweaved fingers varies in width in a direction of propagation current thereby resulting in a difference of resistance within each of the interweaved fingers in the direction of propagation of current; a second layer arranged below the first layer. The second layer compensates for the difference of resistance in the first layer.

For example, a semiconductor device includes an output electrode to be connected to an inductive load, a ground electrode to be connected to a ground terminal, first and second transistors connected in parallel between the output and ground electrodes, an active clamp circuit connected to the gate of the first transistor, and a gate control circuit to control the gates of the first and second transistors to keep the first and second transistors on in a first operation state and off in a second operation state. After a transition from the first operation state to the second, before the active clamp circuit operates, the gate control circuit short-circuits between the gate and source of the second transistor.

A transient voltage suppressor is disclosed that includes an electrode, a substrate disposed on the electrode, the substrate having a first doping, an epitaxial layer disposed on the substrate, the epitaxial layer having a second doping that is different from the first doping, a channel formed in the epitaxial layer having a width W, a length L and a plurality of curved regions, the channel forming a plurality of adjacent sections, the channel having a third doping that is different from the first doping and the second doping and a metal layer formed on top of the channel and contained within the width W of the channel.

A transient voltage suppression device includes: a substrate; a first conductive type well region including a first well and a second well; a second conductive type well region including a third well and a fourth well, the third well being disposed between the first well and the second well so as to isolate the first well and the second well, and the second well being disposed between the third well and the fourth well; a zener diode active region; a first doped region, provided in the first well; a second doped region, provided in the first well; a third doped region, provided in the second well; a fourth doped region, provided in the second well; a fifth doped region, provided in the zener diode active region; and a sixth doped region, provided in the zener diode active region.

A semiconductor device which includes two or more integrated deep trench features configured as a Zener diode. The Zener diode includes a plurality of deep trenches extending into semiconductor material of the substrate and a dielectric deep trench liner that includes a dielectric material. The deep trench further includes a doped sheath contacting the deep trench liner and an electrically conductive deep trench filler material within the deep trench. The doped sheath of adjacent deep trenches overlap and form a region of higher doping concentration which sets the breakdown voltage of the Zener diode. The Zener diode can be used as a triggering diode to limit the voltage on other components in a semiconductor device.

A semiconductor device includes a semiconductor layer, a transistor cell portion, formed in the semiconductor layer, a first trench, formed in the semiconductor layer, a diode, electrically separated from the transistor cell portion and having a first conductivity type portion and a second conductivity type portion disposed inside the first trench, a second trench, formed in the semiconductor layer, and a bidirectional Zener diode, electrically connected to the transistor cell portion and having a pair of first conductivity type portions, disposed inside the second trench, and at least one second conductivity type portion, formed between the pair of first conductivity type portion.

A method for manufacturing a Zener diode includes implanting an N-type Buried Layer (NBL) with an N-type dopant in a first epitaxial layer, wherein the NBL comprises an NBL opening excluding the N-type dopant. A P-type Buried Layer (PBL) having a peak PBL doping concentration below the NBL is implanted. A second epitaxial layer is grown over the NBL. A P-type region (Plink) is implanted to couple to the PBL above the NBL opening, and to couple the Plink to an Anode electrode. An N-type region (Nlink) is implanted to couple the NBL to a Cathode electrode.

A power device which is formed on a semiconductor substrate includes: a lateral insulated gate bipolar transistor (LIGBT), a PN diode and a clamp diode. The PN diode is connected in parallel to the LIGBT. The clamp diode has a clamp forward terminal and a clamp reverse terminal, which are electrically connected to a drain and a gate of the LIGBT, to clamp a gate voltage applied to the gate not to be higher than a predetermined voltage threshold.

A transient voltage suppressor is disclosed that includes an electrode, a substrate disposed on the electrode, the substrate having a first doping, an epitaxial layer disposed on the substrate, the epitaxial layer having a second doping that is different from the first doping, a channel formed in the epitaxial layer having a width W, a length L and a plurality of curved regions, the channel forming a plurality of adjacent sections, the channel having a third doping that is different from the first doping and the second doping and a metal layer formed on top of the channel and contained within the width W of the channel.