Embodiments are provided herein for low loss coupling capacitor structures. The embodiments include a n-type varactor (NVAR) configuration and p-type varactor (PVAR) configuration. The structure in the NVAR configuration comprises a p-doped semiconductor substrate (Psub), a deep n-doped semiconductor well (DNW) in the Psub, and a p-doped semiconductor well (P well) in the DNW. The circuit structure further comprises a source terminal of a p-doped semiconductor material within P well, and a drain terminal of the p-doped semiconductor material within the P well. Additionally, the circuit structure comprises an insulated gate on the surface of the P well, a metal pattern comprising a plurality of layers of metal lines, and a plurality of vias through the metal lines. The vias are contacts connecting the metal lines to the gate, the source terminal, and the drain terminal.

An integrated circuit includes a first semiconductor well contained in a semiconductor substrate and a second semiconductor well contained in the first semiconductor well. A capacitive element for the integrated circuit includes a first electrode and a second electrode, where the first electrode includes at least one vertical conductive structure filling a trench extending vertically into the first semiconductor well. The vertical conductive structure is electrically isolated from the first semiconductor well by a dielectric envelope covering a base and the sides of the trench. The vertical conductive structure penetrates into the second semiconductor well at least at one longitudinal end of the trench. The second electrode includes the first semiconductor well and the second semiconductor well.

A method of manufacturing a capacitor structure is provided, including the following steps. A substrate is provided. A first doped silicon material layer is formed on the substrate. A surface flattening process is performed on the first doped silicon material layer through a plasma treatment. An insulating material layer is formed on the first doped silicon material layer after the surface flattening process is performed. A second doped silicon material layer is formed on the insulating material layer. The first doped silicon material layer is patterned into a first electrode. The insulating material layer is patterned into an insulating layer. The second doped silicon material layer is patterned into a second electrode. The method of manufacturing the capacitor structure may be used to produce a capacitor with better reliability and may improve capacitance density.

Embodiments are provided herein for low loss coupling capacitor structures. The embodiments include a n-type varactor (NVAR) configuration and p-type varactor (PVAR) configuration. The structure in the NVAR configuration comprises a p-doped semiconductor substrate (Psub), a deep n-doped semiconductor well (DNW) in the Psub, and a p-doped semiconductor well (P well) in the DNW. The circuit structure further comprises a source terminal of a p-doped semiconductor material within P well, and a drain terminal of the p-doped semiconductor material within the P well. Additionally, the circuit structure comprises an insulated gate on the surface of the P well, a metal pattern comprising a plurality of layers of metal lines, and a plurality of vias through the metal lines. The vias are contacts connecting the metal lines to the gate, the source terminal, and the drain terminal.

The present disclosure provides a method for manufacturing semiconductor element. The method includes: a first masking process, forming a resist layer on the surface of the substrate; a channel forming process, implanting impurities with the same polarity as a well of an FET region into the surface of the substrate, and forming a channel region for the well of the FET region; a gate forming process, forming gates G respectively on the well of the FET region and the well of the variable-capacitance diode region separated by insulating films; a second masking process, generating a second implantation barrier layer on the surface of the substrate; and an epitaxy forming process, implanting impurities with the opposite polarity to that of the well of the FET region into the surface of the substrate, and forming an epitaxy region for the well of the FET region.

The present disclosure provides a method for manufacturing semiconductor element. The method includes: a first masking process, forming a resist layer on the surface of the substrate; a channel forming process, implanting impurities with the same polarity as a well of an FET region into the surface of the substrate, and forming a channel region for the well of the FET region; a gate forming process, forming gates G respectively on the well of the FET region and the well of the variable-capacitance diode region separated by insulating films; a second masking process, generating a second implantation barrier layer on the surface of the substrate; and an epitaxy forming process, implanting impurities with the opposite polarity to that of the well of the FET region into the surface of the substrate, and forming an epitaxy region for the well of the FET region.

An integrated circuit includes an SOI substrate having a semiconductor layer over a buried insulator layer; the semiconductor layer contains white space regions that include a PWELL region. An electronic device includes an NWELL region in the semiconductor layer, a dielectric over the NWELL region, and a polysilicon plate over the dielectric. A sacrificial NWELL ring is adjacent to and separated from the NWELL region by a first gap.

An integrated circuit includes a substrate having a first conductivity type. A well formed at an upper surface has a second, opposite conductivity type and a first dopant concentration. First and second STI structures are formed and a polysilicon gate structure is formed between the first and second STI structures. The polysilicon gate structure extends over a first side of the first STI structure and over a first side of the second STI structure. A first doped region is formed within the well at the upper surface and on a second side of the first STI structure and a second doped region is formed within the well at the upper surface and on a second side of the second STI structure. The first and second doped regions each have the second conductivity type and a second dopant concentration that is greater than the first dopant concentration.

This disclosure illustrates a FinFET based dual electronic component that may be used as a capacitor or a resistor and methods to manufacture said component. A FinFET based dual electronic component comprises a fin, source and drain regions, a gate dielectric, and a gate. The fin is heavily doped such that semiconductor material of the fin becomes degenerate.

An image sensing device is provided to include a pixel region and a peripheral region located outside of the pixel region. The peripheral region includes logic circuits located to receive a pixel signals from the pixel region and configured to process the pixel signals and a capacitor located adjacent to the logic circuits. The capacitor includes an active region, a recessed structure, and a first junction. The active region includes a first impurity region and a second impurity region formed over the first impurity region. The recessed structure is at least partly disposed in the active region and including a first portion disposed in the active region and including a conductive material and a second portion surrounding the first portion and including an insulation material. The first junction is formed in the active region and spaced apart from the recessed structure by a predetermined distance.