A manufacturing method for a semiconductor element includes a step of forming a mask partly having an opening and configured to cover a surface of a base substrate, and a step of forming a semiconductor layer containing a predetermined semiconductor material by inducing epitaxial growth along the mask from the surface of the base substrate exposed from an opening. A surface on the side closer to the semiconductor layer in the mask is formed of an amorphous first material that does not contain an element to serve as a donor or an acceptor in the predetermined semiconductor material.

A low turn-on voltage GaN diode having an anode metal with a consistent crystal orientation and a preparation method thereof. The low turn-on voltage GaN diode having an anode metal with a consistent crystal orientation provided by the present disclosure includes a substrate layer, a GaN buffer layer, a GaN channel layer and an AlGaN barrier layer, which are arranged in sequence from bottom to top; a cathode arranged on the AlGaN barrier layer; a groove arranged in the GaN channel layer and the AlGaN barrier layer, and an anode provided on a bottom and a side wall of the groove and part of the AlGaN barrier layer; a dielectric layer provided on an uncovered portion of the AlGaN barrier layer; wherein, a contact portion of the anode with the groove and the AlGaN barrier layer is W or Mo metal with a crystal orientation of <100>.

Methods and semiconductor devices are provided. A vertical junction field effect transistor (JFET) includes a substrate, an active region having a plurality of semiconductor fins, a source metal layer on an upper surface of the fins, a source metal pad layer coupled to the semiconductor fins through the source metal layer, a gate region surrounding the semiconductor fins, and a body diode surrounding the gate region.

A device includes a diode that includes a first group III-nitride (III-N) material and a transistor adjacent to the diode, where the transistor includes the first III-N material. The diode includes a second III-N material, a third III-N material between the first III-N material and the second III-N material, a first terminal including a metal in contact with the third III-N material, a second terminal coupled to the first terminal through the first group III-N material. The device further includes a transistor structure, adjacent to the diode structure. The transistor structure includes the first, second, and third III-N materials, a source and drain, a gate electrode and a gate dielectric between the gate electrode and each of the first, second and third III-N materials.

A Group III-Nitride (III-N) device structure is provided which comprises: a heterostructure having three or more layers comprising III-N material, an anode within a recess that extends through two or more of the layers, wherein the anode is in electrical contact with the first layer, a cathode comprising donor dopants, wherein the cathode is on the first layer of the heterostructure; and a conducting region in the first layer in direct contact to the cathode and conductively connected to the anode. Other embodiments are also disclosed and claimed.

Provided are a Schottky diode and a manufacturing method therefor. The Schottky diode (100) includes a nitride channel layer (1); a nitride barrier layer (2) formed on the nitride channel layer (1); a nitride cap layer (3) formed on the nitride barrier layer (2), wherein the nitride cap layer (3) includes an active region (31) and an inactive region (32); a passivation layer (4) formed on the nitride cap layer (3), where the passivation layer (4) includes a first groove penetrating through the passivation layer (4) to expose the nitride cap layer (3), and the first groove corresponds to the active region (31); a dielectric layer (5) located on the passivation layer (4) and an inner wall of the first groove, wherein the dielectric layer (5) forms a second groove, and the dielectric layer (5) includes a third groove penetrating through the dielectric layer (5) to expose a part of the active region (31) of the nitride cap layer (3); and an anode layer (6) formed in the second groove and the third groove and in contact with the active region (31).

Provided are a diode and a manufacturing method therefor. The diode includes: a nitride channel layer; a nitride barrier layer, formed on the nitride channel layer; an oxidation forming layer, wherein a part of the oxidation forming layer is positioned in the nitride barrier layer, and a surface of the oxidation forming layer away from the nitride channel layer is flush with a surface of the nitride barrier layer away from the nitride channel layer; a passivation layer, formed on the nitride barrier layer, wherein the passivation layer includes a first groove penetrating through the passivation layer to expose the oxidation forming layer and a part of the nitride barrier layer; and a first electrode, formed in the first groove, wherein the first electrode is in contact with the nitride barrier layer and the oxidation forming layer.

The present disclosure provides a method for manufacturing vertical device. The method includes: forming a plurality of first grooves in the front side of the N-type heavily doped layer; forming an N-type lightly doped layer in the plurality of first grooves and on the front side of the N-type heavily doped layer; forming second grooves in the N-type lightly doped layer; forming a P-type semiconductor layer in the second grooves and on the front side of the N-type lightly doped layer; planarizing the P-type semiconductor layer; forming a passivation layer on the planarized structure; forming a third groove in the passivation layer, wherein the third groove has a depth equal to a thickness of the passivation layer; and forming a first electrode and a second electrode.

Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device having a channel area including a channel III-V material, and a source area including a first portion and a second portion of the source area. The first portion of the source area includes a first III-V material, and the second portion of the source area includes a second III-V material. The channel III-V material, the first III-V material and the second III-V material may have a same lattice constant. Moreover, the first III-V material has a first bandgap, and the second III-V material has a second bandgap, the channel III-V material has a channel III-V material bandgap, where the channel material bandgap, the second bandgap, and the first bandgap form a monotonic sequence of bandgaps. Other embodiments may be described and/or claimed.

A piezo-junction device may be provided. The piezo-junction device comprises a piezoelectric element comprising two electrodes and piezoelectric material in-between, and a semiconductor junction device adjacent to the piezoelectric element such that one of the two electrodes of the piezoelectric element is in contact with the semiconductor junction device connecting the semiconductor junction device and the piezoelectric element electrically in series. Thereby, the semiconductor junction device and the piezoelectric element are together positioned in a fixed mechanical clamp such that the piezoelectric element with an applied electrical field applies strain to the semiconductor junction device causing a change in Fermi levels of the semiconductor junction device.