A MOS controlled thyristor device according to the concept of the present invention includes a substrate comprising a first surface and a second surface, which face each other, gate patterns disposed on the first surface, a cathode electrode configured to cover the gate patterns, and an anode electrode disposed on the second surface, The substrate includes a lower emitter layer having a first conductive type, a lower base layer having a second conductive type on the lower emitter layer, an upper base region provided in an upper portion of the lower emitter layer and having a first conductive type, wherein the upper base region is configured to expose a portion of a top surface of the lower base layer, an upper emitter region having a second conductive type and provided in an upper portion of the upper base region, a first doped region having a first conductive type and a second doped region surrounded by the first doped region and having a second conductive type, wherein the first and second doped regions are provided in an upper portion of the upper emitter region, and a first doping pattern having a first conductive type, which is provided on one surface of the upper portion of the upper emitter region. The first doping pattern is interposed between the upper base region and the first doped region along a first direction parallel to the top surface of the substrate. The first doping pattern is configured to expose a top surface of the upper emitter region on the other surface of the upper portion of the upper emitter region. Each of the gate patterns is configured to cover portions of an exposed top surface of the lower base layer, an exposed top surface of the upper base layer, an exposed top surface of the upper emitter region, a top surface of the first doping pattern, and a top surface of the first doped region. The cathode electrode is configured to cover portions of top and side surfaces of the gate pattern, a top surface of the second doped region, and a top surface of the first doped region. The first conductive type and the second conductive type are different from each other.

The present invention forms an off-FET channel having a uniform and short length by using a self-align process of a method of forming and recessing a spacer, thereby enhancing the current driving capability of an off-FET and the uniformity of a device operation.

The present invention forms an off-FET channel having a uniform and short length by using a self-align process of a method of forming and recessing a spacer, thereby enhancing the current driving capability of an off-FET and the uniformity of a device operation.

A semiconductor device includes a substrate, a buffer layer disposed on the substrate, a barrier layer disposed on the buffer layer, a source, a drain, and a gate stack. The source, the drain, and the gate stack are disposed on the barrier layer. The gate stack includes a first epitaxial layer on the barrier layer, a second epitaxial layer on the first epitaxial layer, and a third epitaxial layer on the second epitaxial layer. The semiconductor device further includes a gate disposed on the gate stack.

A MOS controlled thyristor device according to the concept of the present invention includes a substrate comprising a first surface and a second surface, which face each other, gate patterns disposed on the first surface, a cathode electrode configured to cover the gate patterns, and an anode electrode disposed on the second surface, The substrate includes a lower emitter layer having a first conductive type, a lower base layer having a second conductive type on the lower emitter layer, an upper base region provided in an upper portion of the lower emitter layer and having a first conductive type, wherein the upper base region is configured to expose a portion of a top surface of the lower base layer, an upper emitter region having a second conductive type and provided in an upper portion of the upper base region, a first doped region having a first conductive type and a second doped region surrounded by the first doped region and having a second conductive type, wherein the first and second doped regions are provided in an upper portion of the upper emitter region, and a first doping pattern having a first conductive type, which is provided on one surface of the upper portion of the upper emitter region. The first doping pattern is interposed between the upper base region and the first doped region along a first direction parallel to the top surface of the substrate. The first doping pattern is configured to expose a top surface of the upper emitter region on the other surface of the upper portion of the upper emitter region. Each of the gate patterns is configured to cover portions of an exposed top surface of the lower base layer, an exposed top surface of the upper base layer, an exposed top surface of the upper emitter region, a top surface of the first doping pattern, and a top surface of the first doped region. The cathode electrode is configured to cover portions of top and side surfaces of the gate pattern, a top surface of the second doped region, and a top surface of the first doped region. The first conductive type and the second conductive type are different from each other.

Methods, apparatus, and processor-readable storage media for automatically limiting power consumption by devices using infrared or radio communications are provided herein. An example computer-implemented method includes detecting, via at least one photodiode of an emitting sensor, one or more signals output by a user device within a predetermined proximity; automatically transitioning, via utilizing at least one transistor connected to the photodiode, and in response to detecting the one or more signals, the emitting sensor from a first power-consumption state to a second power-consumption state; transmitting one or more signals in response to transitioning from the first power-consumption state to the second power-consumption state; and subsequent to transmitting, automatically transitioning, via utilizing the at least one transistor, the emitting sensor from the second power-consumption state to the first power-consumption state after a predetermined amount of time has elapsed during which no signals were detected.

Methods, apparatus, and processor-readable storage media for automatically limiting power consumption by devices using infrared or radio communications are provided herein. An example computer-implemented method includes detecting, via at least one photodiode of an emitting sensor, one or more signals output by a user device within a predetermined proximity; automatically transitioning, via utilizing at least one transistor connected to the photodiode, and in response to detecting the one or more signals, the emitting sensor from a first power-consumption state to a second power-consumption state; transmitting one or more signals in response to transitioning from the first power-consumption state to the second power-consumption state; and subsequent to transmitting, automatically transitioning, via utilizing the at least one transistor, the emitting sensor from the second power-consumption state to the first power-consumption state after a predetermined amount of time has elapsed during which no signals were detected.

A transistor device having reduced electrical field at the gate oxide interface is disclosed. In one embodiment, the transistor device comprises a gate, a source, and a drain, wherein the gate is at least partially in contact with a gate oxide. The transistor device has a P+ region within a JFET region of the transistor device in order to reduce an electrical field on the gate oxide.

An insulated gate turn-off thyristor has a layered structure including a p+ layer (e.g., a substrate), an n-epi layer, a p-well, vertical insulated gate regions formed in the p-well, and an n layer over the p-well and between the gate regions, so that vertical npn and pnp transistors are formed. After forming the p-well, boron ions are implanted into the exposed surface of the p-well to form a p+ region. The n-epi layer is then grown over the p-well and the p+ region, and the boron in the p+ region is diffused upward into the n-epi layer and downward to form an intermediate p+ region. The p-well's highly doped intermediate region enables improvement in the npn transistor efficiency as well as enabling more independent control over the characteristics of the n-type layer (emitter) and the overall dopant concentration and thickness of the p-type base to optimize the thyristor's performance.

A semiconductor device includes a substrate having a cell region and a peripheral region, a thyristor on the cell region, a MOS transistor on the peripheral region, and a first silicide layer on the substrate adjacent to the thyristor on the cell region. Preferably, the thyristor includes: a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a fourth semiconductor layer on the cell region, vertical dielectric patterns in the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer, and first contact plugs on the fourth semiconductor layer.