A gate-turn-off thyristor is provided. The gate-turn-off thyristor includes a plurality of strips formed by repeatedly arranging a plurality of N-type emitter regions with high doping concentration of an upper transistor on an upper surface of an N-type silicon substrate with high resistivity, wherein a periphery of each strip of the plurality of strips is surrounded with a P-type dense base region bus bar of the upper transistor, a cathode metal layer is disposed on an N-type emitter region of the plurality of N-type emitter regions of the upper transistor, and a P-type base region of the upper transistor is disposed below the N-type emitter region of the upper transistor; a side of the P-type base region of the upper transistor is connected to a P-type dense base region of the upper transistor or a P-type dense base region bus bar of the upper transistor.

A semiconductor structure for a DRAM is described having multiple layers of arrays of memory cells. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Select transistors enable the use of folded bit lines. The memory cells preferably are thyristors. Methods of fabricating the array are described.

A method for producing an edge structure of a semiconductor component includes: providing a semiconductor body having at least two mutually spaced-apart main faces respectively having an edge, between which edges an edge face extends; and etching a predetermined edge contour by purposely applying a chemical etchant onto the edge face by an etchant jet with simultaneous rotation of the semiconductor body about a rotation axis. The etchant jet is guided with a predetermined jet cross section, while being directed tangentially with respect to the edge face, such that the etchant jet impinges on the edge face only with a part of the jet cross section. A corresponding device for producing an edge structure of a semiconductor component is also described.

A device includes a semiconductor substrate. A step is formed at a periphery of the semiconductor substrate. A first layer, made of polysilicon doped in oxygen, is deposited on top of and in contact with a first surface of the substrate. This first layer extends at least on a wall and bottom of the step. A second layer, made of glass, is deposited on top of the first layer and the edges of the first layer. The second layer forms a boss between the step and a central area of the device.

A sacrificial substrate wafer is provided. A low resistivity etch stop layer is formed on or in the top surface of the wafer. The etch stop layer may be a highly doped, p+ type epitaxially grown layer, or an implanted p+ type boron layer, or an epitaxially grown p+ type SiGe layer. Various epitaxial layers, such as an n− type drift layer, and doped regions are then formed over the etch stop layer to form a vertical power device. The starting wafer is then removed by a combination of mechanical grinding/polishing to leave a thinner layer of the starting wafer. A chemical or plasma etch is then used to remove the remainder of the starting wafer, using the etch stop layer to automatically stop the etching. A bottom metal electrode is then formed on the etch stop layer. The etch stop layer injects hole carriers into the drift layer.

After the various regions of a vertical power device are formed in or on the top surface of an n-type wafer, the wafer is thinned, such as by grinding. A drift layer may be n-type, and various n-type regions and p-type regions in the top surface contact a top metal electrode. A blanket dopant implant through the bottom surface of the thinned wafer is performed to form an n− buffer layer and a bottom p+ emitter layer. Energetic particles are injected through the bottom surface to intentionally damage the crystalline structure. A wet etch is performed, which etches the damaged crystal at a much greater rate, so some areas of the n− buffer layer are exposed. The bottom surface is metallized. The areas where the metal contacts the n− buffer layer form cathodes of an anti-parallel diode for conducting reverse voltages, such as voltage spikes from inductive loads.

A semiconductor structure for a DRAM is described having multiple layers of arrays of memory cells. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Select transistors enable the use of folded bit lines. The memory cells preferably are thyristors. Methods of fabricating the array are described.

The present invention forms an off-FET channel having a uniform and short length by using a self-align process of a method of forming and recessing a spacer, thereby enhancing the current driving capability of an off-FET and the uniformity of a device operation.

An integrated gate-commutated thyristor (IGCT) includes a semiconductor wafer having a first main side and a second main side opposite to the first main side and a plurality of first type thyristor cells and second type thyristor cells. The cathode electrode of the first type thyristor cells forms an ohmic contact with the cathode region and the cathode electrode of the second type thyristor cells is insulated from the cathode region. A predefined percentage of second type thyristor cells of the overall amount of first type thyristor cells and second type thyristor cells in a segment ring is greater than .sub.0% and less than or equal to 75%.

Protection against electrostatic discharges is to be improved for electronic devices, or is to be provided in the first place. The device for protection against electrostatic discharges having an integrated semiconductor protection device comprises an inner region (1) configured at least as a thyristor (SCR) and at least one outer region (2a, 2b) configured as a corner region, which is formed and configured at least as a PNP transistor. The inner region (1) and the at least one outer region (2a, 2b) are arranged adjacent to one another.