Bi-directional trench power switches. At least one example is a semiconductor device comprising: an upper base region associated with a first side of a substrate of semiconductor material; an upper-CE trench defined on the first side, the upper-CE trench defines a proximal opening at the first side and a distal end within the substrate; an upper collector-emitter region disposed at the distal end of the upper-CE trench; a lower base region associated with a second side of substrate; and a lower collector-emitter region associated with the second side.

The present application teaches, among other innovations, power semiconductor devices in which breakdown initiation regions, on BOTH sides of a die, are located inside the emitter/collector regions, but laterally spaced away from insulated trenches which surround the emitter/collector regions. Preferably this is part of a symmetrically-bidirectional power device of the “B-TRAN” type. In one advantageous group of embodiments (but not all), the breakdown initiation regions are defined by dopant introduction through the bottom of trench portions which lie within the emitter/collector region. In one group of embodiments (but not all), these can advantageously be separated trench portions which are not continuous with the trench(es) surrounding the emitter/collector region(s).

The application provides a SCR and a manufacturing method thereof. The SCR comprises: a P-type heavily doped region 20 and an N-type heavily doped region 28 forming an anode formed on the upper part of an N-type well 60, a P-type heavily doped region 26 and an N-type heavily doped region 24 forming a cathode formed on the upper part of a P-type well 70, an active region of the N-type well 60 is between the N-type heavily doped region 28 and an interface of the N-type well 60 and the P-type well 70, a STI is provided between the N-type heavily doped region 24 and the interface, the STI is adjacent to the N-type heavily doped region 24, and an active region of the P-type well 70 is provided between the STI and the interface. The present application can improve trigger voltage of the SCR and save layout area.

A first silicon controlled rectifier has a breakdown voltage in a first direction and a breakdown voltage in a second direction. A second silicon controlled rectifier has a breakdown voltage with a higher magnitude than the first silicon controlled rectifier in the first direction, and a breakdown voltage with a lower magnitude than the first silicon controlled rectifier in the second direction. A bidirectional electrostatic discharge (ESD) structure utilizes both the first silicon controlled rectifier and the second silicon controlled rectifier to provide bidirectional protection.

The present disclosure provides a silicon controlled rectifier and a manufacturing method thereof. The silicon controlled rectifier comprises: an N-type well 60, an upper portion of which is provided with a P-type heavily doped region 20 and an N-type heavily doped region 28; an N-type well 62, an upper portion of which is provided with a P-type heavily doped region 22 and an N-type heavily doped region 26; and a P-type well 70 connecting the N-type well 60 and 62, an upper portion of which is provided with a P-type heavily doped region 24; wherein a first electrode structure is in mirror symmetry with a second electrode structure with respect to the P-type heavily doped region 24, and active regions of the N-type well 60 and 62 are respectively provided between the P-type heavily doped region 24 and each of the N-type heavily doped region 28 and 26.

A device includes a semiconductor substrate. A step is formed at a periphery of the semiconductor substrate. A first layer, made of polysilicon doped in oxygen, is deposited on top of and in contact with a first surface of the substrate. This first layer extends at least on a wall and bottom of the step. A second layer, made of glass, is deposited on top of the first layer and the edges of the first layer. The second layer forms a boss between the step and a central area of the device.

An ESD protection device may include a substrate having first and second substrate layers, and first and second bridged regions. Each substrate layer may include first and second border regions and a middle region laterally therebetween. Each bridged region may be arranged within the middle region and a respective border region of the second substrate layer. The middle region of the second substrate layer may be laterally narrower than the middle region of the first substrate layer. Each border region of the second substrate layer may be partially arranged over the middle region of the first substrate layer and partially arranged over a respective border region of the first substrate layer. The border regions of the substrate layers, and the bridged regions may have a first conductivity type, and the middle regions of the substrate layers may have a second conductivity type different from the first conductivity type.

A device includes a semiconductor substrate. A step is formed at a periphery of the semiconductor substrate. A first layer, made of polysilicon doped in oxygen, is deposited on top of and in contact with a first surface of the substrate. This first layer extends at least on a wall and bottom of the step. A second layer, made of glass, is deposited on top of the first layer and the edges of the first layer. The second layer forms a boss between the step and a central area of the device.

A vertical power component includes a doped silicon substrate of a first conductivity type. A local well of a second conductivity type extends from an upper surface of the substrate. A passivation structure coats a peripheral region of the upper surface side of the substrate surrounding the well. This passivation structure includes, on top of and in contact with the peripheral substrate region, a first region made of a first passivation material and a second region made of a second passivation material. The second region generates, in a surface region of the substrate in contact with said second region, a local increase of the concentration of majority carriers in the substrate.

An ESD protection device may include a substrate having first and second substrate layers, and first and second bridged regions. Each substrate layer may include first and second border regions and a middle region laterally therebetween. Each bridged region may be arranged within the middle region and a respective border region of the second substrate layer. The middle region of the second substrate layer may be laterally narrower than the middle region of the first substrate layer. Each border region of the second substrate layer may be partially arranged over the middle region of the first substrate layer and partially arranged over a respective border region of the first substrate layer. The border regions of the substrate layers, and the bridged regions may have a first conductivity type, and the middle regions of the substrate layers may have a second conductivity type different from the first conductivity type.