A nitride semiconductor device includes a substrate, a first electron transport layer above the substrate, a first electron supply layer above the first electron transport layer, a first nitride semiconductor layer above the first electron supply layer, a first opening passing through the first nitride semiconductor layer and the first electron supply layer and reaching the first electron transport layer, a second electron transport layer disposed above the first nitride semiconductor layer and along the inner surface of the first opening, a second electron supply layer disposed above the second electron transport layer and covering the first opening, a gate electrode disposed above the second electron supply layer and covering the first opening, a source electrode connected to the first nitride semiconductor layer and the second electron transport layer, and a drain electrode.

A process of fabricating semiconductor devices includes determining a correlation between band gap and long range order parameter for one or more stoichiometries. Semiconductor materials having a preselected (target) band gap can be fabricated by controlling process parameters to form a material having a stoichiometry and long range order parameter having the target band gap.

A semiconductor device includes a semiconductor element. The semiconductor element has a semiconductor layer, a first-conductivity-type layer, a saturation current suppression layer, a current dispersion layer, a base region, a source region, trench gate structures, an interlayer insulation film, a source electrode, a drain electrode, and a second deep layer. The first-conductivity-type layer is disposed above the semiconductor layer. The saturation current suppression layer disposed above the first-conductivity-type layer includes a first deep layer and a JEFT portion. The base region is disposed above the saturation current suppression layer. The source region and the contact region are disposed above the region. Each of the trench gate structures has a gate trench, a gate insulation film, and a gate electrode. The second deep layer is disposed among the trench gate structures and is connected to the first deep layer.

Organosilicon chemistry, polymer derived ceramic materials, and methods. Such materials and methods for making polysilocarb (SiOC) and Silicon Carbide (SiC) materials having 3-nines, 4-nines, 6-nines and greater purity. Processes and articles utilizing such high purity SiOC and SiC.

A method of fabricating a superconducting device includes determining a target transition temperature and utilizing a predefined quantitative relationship between superconducting transition temperature and an order parameter for at least one superconducting material composition is utilized to select a superconductor material composition that is capable of providing a target transition temperature. Process parameters may be controlled to form a superconductor device comprising at least one superconductor material having a material composition providing the target transition temperature.

A SiC MOSFET device having low specific on resistance is described. The device has N+, P-well and JFET regions extended in one direction (Y-direction) and P+ and source contacts extended in an orthogonal direction (X-direction). The polysilicon gate of the device covers the JFET region and is terminated over the P-well region to minimize electric field at the polysilicon gate edge. In use, current flows vertically from the drain contact at the bottom of the structure into the JFET region and then laterally in the X direction through the accumulation region and through the MOSFET channels into the adjacent N+ region. The current flowing out of the channel then flows along the N+ region in the Y-direction and is collected by the source contacts and the final metal. Methods of making the device are also described.

A field-plate trench FET having a drain region, an epitaxial layer, a source region, a gate conductive layer formed in a trench, a field-plate dielectric layer formed on vertical sidewalls of the trench, a well region formed below the trench, a source contact and a gate contact. When the well region is in direct physical contact with the gate conductive layer, the field-plate trench FET can be used as a normally-on device working depletion mode, and when the well region is electrically isolated from the gate conductive layer by the field-plate layer, the field-plate trench FET can be used as a normally-off device working in an accumulation-depletion mode.

A semiconductor device includes: a channel layer made of GaN; a barrier layer formed on the channel layer, the bather layer being made of AlGaN and having a larger band gap than the channel layer; a p-type GaN layer selectively formed on the barrier layer; a gate electrode made of ITO on the p-type GaN layer; and a source electrode and a drain electrode on regions of the barrier layer laterally outward of the gate electrode. The width of the gate electrode in the gate length direction is smaller than or equal to the width of the p-type GaN layer in the gate length direction, and the difference between the width of the gate electrode in the gate length direction and the width of the p-type GaN layer in the gate length direction is less than or equal to 0.2 μm.

In accordance with the present techniques, there is provided a JFET device structures and methods for fabricating the same. Specifically, there is provided a transistor including a semiconductor substrate having a source and a drain. The transistor also includes a doped channel formed in the semiconductor substrate between the source and the drain, the channel configured to pass current between the source and the drain. Additionally, the transistor has a gate comprising a semiconductor material formed over the channel and dielectric spacers on each side of the gate. The source and the drain are spatially separated from the gate so that the gate is not over the drain and source.

A cell structure for a field effect transistor having same gate and source doping includes: a silicon carbide substrate with a doping type of a first conductivity type; a semiconductor epitaxial layer of the first conductivity type and a first electrode respectively provided on front and back faces of the silicon carbide substrate; and a floating region of a second conductivity type, a gate implantation region of the first conductivity type, and a source implantation region of the first conductivity type sequentially provided on the semiconductor epitaxial layer of the first conductivity type, wherein a gate is provided on the gate implantation region, a source is provided on the source implantation region, an inter-electrode dielectric is provided between the gate implantation region and the source implantation region, and the inter-electrode dielectric is used for isolating the gate from the source.