A two-terminal memory device including: a substrate; a source and a drain formed to face each other on an upper surface of the substrate; a ferroelectric layer connected to the source and the drain and formed between the source and the drain; and an extended drain extending from the drain and laminated on the ferroelectric layer. The two-terminal memory device may be applied as a cross-point type and neuromorphic device capable of implementing multi-resistance levels with multi-layer switchable resistance layers.

Embodiments disclose a semiconductor structure and a method for fabricating the same. The semiconductor structure includes: a substrate, a gate dielectric layer, a first conductive layer, and a conductive plug. The gate dielectric layer is provided on the substrate, and the first conductive layer is provided on the gate dielectric layer. The conductive plug is provided on the gate dielectric layer and covers a side wall of the first conductive layer, where a projection of the conductive plug on the substrate and a projection of the gate dielectric layer on the substrate at least partially overlap. By providing the conductive plug, a breakdown current can break down a region of the gate dielectric layer corresponding to the conductive plug by means of the conductive plug. That is, a breakdown position is adjusted by controlling an overlapping position between the conductive plug and the gate dielectric layer.

A flash memory device includes a substrate, a semiconductor quantum well layer, a semiconductor spacer, a semiconductor channel layer, a gate structure, and source/drain regions. The semiconductor quantum well layer is formed of a first semiconductor material and is disposed over the substrate. The semiconductor spacer is formed of a second semiconductor material and is disposed over the first semiconductor channel layer. The semiconductor channel layer is formed of the first semiconductor material and is disposed over the semiconductor spacer. Thea gate structure is over the second semiconductor channel layer. The source/drain regions are over the substrate and are on opposite sides of the gate structure.

The present application discloses a method for fabricating a semiconductor device The method includes providing a substrate; forming a channel region in the substrate; forming a gate dielectric layer on the channel region; forming a gate bottom conductive layer on the gate dielectric layer; forming first impurity regions on two ends of the channel region; forming first contacts on the first impurity regions; forming programmable insulating layers on the first contacts; forming a gate via on the gate bottom conductive layer; and forming a top conductive layer on the gate via and the programmable insulating layers.

The present disclosure relates to a reconfigurable logic-in-memory device using a silicon transistor, according to the embodiment of the present disclosure, the reconfigurable logic-in-memory device using a silicon transistor comprises the silicon transistor including a drain region, a first channel region, a second channel region, a source region, and a gate region, wherein the silicon transistor performs a first channel operation while forming a first positive feedback loop in which an electron is a majority carrier in the first channel region and the second channel region depending on a level of a gate voltage V.sub.in applied through the gate region or performs a second channel operation while forming a second positive feedback loop in which a hole is a majority carrier in the first channel region and the second channel region depending on the level of a gate voltage V.sub.in applied through the gate region.

Methods of forming a compact FDSOI OTP/MTP cell and a compact FinFET OTP/MTP cell and the resulting devices are provided. Embodiments include forming a SOI region or a fin over a BOX layer over a substrate; forming a first and a second gate stack, laterally separated, over respective portions of the SOI region or the fin; forming a first and a second liner along each first and second sidewall and of the first and the second gate stack, respectively, the second sidewall over respective portions of the SOI region or the fin; forming a spacer on each first and second liner; forming a S/D region in the SOI region or the fin between the first and the second gate stack; forming a CA over the S/D region; utilizing each gate of the first gate stack and the second gate stack as a WL; and connecting a BL to the CA.

A three terminal ReRAM device, which combines a Schottky barrier transistor and a Schottky barrier ReRAM into a single device is provided. The Schottky transistor memory device includes a source region, a drain region, and a gate electrode. Between the source and drain regions, the ReRAM material is present. The ReRAM material can include a metal oxide, such as zinc or hafnium oxide. A Schottky barrier forms naturally between the drain region and the ReRAM material. As voltage is applied to the gate electrode and the source region, the Schottky barrier breaks down, leading to the formation of a filament across the drain region and the ReRAM material. The filament is non-volatile and short-circuits the reverse-biased barrier, keeping the device in a low resistance state. The filament can be removed by reversing the polarity of the voltage such that the device switches back to a high resistance state.

The present disclosure generally relates to an apparatus for high density memory with integrated logic. A three terminal ReRAM device, which includes a p-n junction and a Schottky barrier, that can switch from a low resistive state to a high resistive state is provided. The Schottky transistor memory device includes a source region, a drain region, a first p-type or n-type oxide layer disposed between the source and drain regions, a second p-type or n-type oxide layer, and a gate electrode. As voltage is applied to the gate electrode, the Schottky barrier breaks down, leading to the formation of a filament. The filament is non-volatile and short-circuits the reverse-biased barrier, keeping the device in a low resistance state. Removing the filament by reversing the polarity of the voltage switches the device back to a high resistance state, allowing for the memory state to be readout through the gate electrode.

There is provided a non-volatile memory device comprising: a substrate; a lower electrode disposed on the substrate; a resistance layer disposed on the lower electrode; and an upper electrode disposed on the resistance layer, wherein the resistance layer include a stack of a graphene oxide film and an iron oxide film, wherein a resistance value of the resistance layer varies based on a voltage applied to the upper electrode.

Disclosed are a memory device including a vertical stack structure and a method of manufacturing the memory device. The memory device includes an insulating structure having a shape including a first surface and a protrusion portion protruding in a first direction from the first surface, a recording material layer covering the protrusion portion along a protruding shape of the protrusion portion and extending to the first surface on the insulating structure a channel layer on the recording material layer along a surface of the recording material layer, a gate insulating layer on the channel layer, and a gate electrode formed at a location on the gate insulating layer to face a second surface which is a protruding upper surface of the protrusion portion, wherein a void exists between the gate electrode and the insulating structure, defined by the insulating structure and the recording material layer.