An integrated circuit includes a bipolar transistor, e.g. a back-ballasted NPN, that can conduct laterally and vertically. At a low voltage breakdown and low current conduction occur laterally near a substrate surface, while at a higher voltage vertical conduction occurs in a more highly-doped channel below the surface. A relatively high-resistance region at the surface has a low doping level to guide the conduction deeper into the collector.

An integrated circuit includes an N-type laterally diffused metal-oxide semiconductor (NLDMOS) transistor including an active semiconductor substrate region having P-type conductivity. The integrated circuit further includes a buried semiconductor region having N+-type conductivity underneath the active substrate region. The buried semiconductor region is more heavily doped than the active semiconductor substrate region.

An integrated circuit includes an N-type laterally diffused metal-oxide semiconductor (NLDMOS) transistor including an active semiconductor substrate region having P-type conductivity. The integrated circuit further includes a buried semiconductor region having N+-type conductivity underneath the active substrate region. The buried semiconductor region is more heavily doped than the active semiconductor substrate region.

A Darlington pair sensor is disclosed. The Darlington pair sensor has an amplifying/horizontal bipolar junction transistor (BJT) and a sensing/vertical BJT and can be used as a biosensor.

The amplifying bipolar junction transistor (BJT) is horizontally disposed on a substrate. The amplifying BJT has a horizontal emitter, a horizontal base, a horizontal collector, and a common extrinsic base/collector. The common extrinsic base/collector is an extrinsic base for the amplifying BJT.

The sensing BJT has a vertical orientation with respect to the amplifying BJT. The sensing BJT has a vertical emitter, a vertical base, an extrinsic vertical base, and the common extrinsic base/collector (in common with the amplifying BJT). The common extrinsic base/collector acts as the sensing BJT collector. The extrinsic vertical base is separated into a left extrinsic vertical base and a right extrinsic vertical base giving the sensing BJT has two separated (dual) bases, a sensing base and a control base.

The Darlington pair sensor has high in-situ signal amplification with low noise and uses substrate space effectively.

A disclosed structure includes a fin-based bipolar junction transistor (BJT) with reduced base resistance. The BJT includes one or more semiconductor fins. Each semiconductor fin has opposing sidewalls, a first width, and a base recess, which extends across the first width through the opposing sidewalls. The BJT includes a base region positioned laterally between collector and emitter regions. The base region includes a base semiconductor layer (e.g., an intrinsic base layer), which fills the base recess and which has a second width greater than the first width such that the base semiconductor layer extends laterally beyond the opposing sidewalls. In a BJT with multiple semiconductor fins, the base recess on each semiconductor fin is filled with a discrete base semiconductor layer. The base region further includes an additional base semiconductor layer (e.g., an extrinsic base layer) covering the base semiconductor layer(s). Also disclosed is a method of forming the structure.

Provided is field-effect transistor structure including: a substrate including therein at least one 1.sup.st doped region, a 2.sup.nd doped region on one side of the 1.sup.st doped region, and a 3.sup.rd doped region on another side of the 1.sup.st doped region; a 1.sup.st channel structure including therein a 4.sup.th doped region on the 2.sup.nd doped region in the substrate; and a 2.sup.nd channel structure, at a side of the 1.sup.st channel structure, including therein a 5.sup.th doped region on the 3.sup.rd doped region in the substrate, wherein the 4.sup.th, 2.sup.nd, 1.sup.st, 3.sup.rd and 5.sup.th doped regions form a sequentially connected passive device.

In a described example, a bipolar junction transistor includes a substrate. An emitter region, a base region, and a collector region are each formed in the substrate. A gate-type structure is formed on the substrate between the base region and the emitter region. A contact is coupled to the gate-type structure, and the contact is adapted to be coupled to a source of DC voltage.

An article of manufacture, having a semiconductor layer and a dielectric layer. The semiconductor layer comprising a first surface and a second surface. The dielectric layer located adjacent to the first surface of the semiconductor layer. One or more base portions of the semiconductor in direct contact with and extending from the dielectric layer. One or more collector portions of the semiconductor in direct contact with and extending from the dielectric layer. One or more emitter portions of the semiconductor in direct contact with and extending from the dielectric layer. The one or more collector portions are spaced apart from the one or more emitter portions by the one or more base portions.

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.

A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.