A silicon carbide semiconductor device includes first semiconductor areas and second semiconductor areas. The first semiconductor areas have a first semiconductor layer of a second conductivity type, a second semiconductor layer of a first conductivity type, first semiconductor regions of the second conductivity type, second semiconductor regions of the first conductivity type, gate electrodes, and first electrodes. The second semiconductor areas have the first semiconductor layer, the second semiconductor layer, third semiconductor regions of the second conductivity type, the gate electrodes, and the first electrodes. The first semiconductor regions include low- impurity-concentration regions and high-impurity-concentration regions. The third semiconductor regions have a potential equal to that of the first electrodes. The first semiconductor regions are connected to the third semiconductor regions by MOS structures. In the first semiconductor regions, the high-impurity-concentration regions are provided at positions different from positions facing the first electrodes.

A semiconductor die with high-voltage tolerant electrical overstress circuit architecture is disclosed. One embodiment of the semiconductor die includes a signal pad, a ground pad, a core circuit electrically connected to the signal pad, and a stacked thyristor protection device. The stacked thyristor includes a first thyristor and a resistive thyristor electrically connected in a stack between the signal pad and the ground pad, which enhances the holding voltage of the circuit relatively to an implementation with only the thyristor. Further, the resistive thyristor includes a PNP bipolar transistor and a NPN bipolar transistor that are cross-coupled, and an electrical connection between a collector of the PNP bipolar transistor and a collector of the NPN bipolar transistor. This allows the resistive thyristor to exhibit both thyristor characteristics and resistive characteristics based on a level of current flow.

An electrostatic discharge (ESD) protection device includes a pad, a diode, a gate ground NMOS (GGNMOS) transistor and a thyristor. The diode includes an anode connected with the pad. The GGNMOS transistor is connected between a cathode of the diode and a ground terminal. The thyristor is formed between the diode and the ground terminal when an ESD current may flow from the pad.

An object is to provide a technique capable of improving both recovery loss and recovery capability. The semiconductor device includes a base layer of a second conductive type disposed on a front surface side of the semiconductor substrate in the IGBT region and an anode layer of a second conductive type disposed on a front surface side of the semiconductor substrate in the diode region. The anode layer includes a first portion having a lower end located at a same position as a lower end of the base layer or having a lower end located above the lower end of the base layer and a second portion adjacent to the first portion in plan view, and whose lower end is located above the lower end of the first portion.

An electrostatic discharge (ESD) protection device includes a pad, a diode, a gate ground NMOS (GGNMOS) transistor and a thyristor. The diode includes an anode connected with the pad. The GGNMOS transistor is connected between a cathode of the diode and a ground terminal. The thyristor is formed between the diode and the ground terminal when an ESD current may flow from the pad.

In an insulated trench gate device, polysilicon in the trench is etched below the top surface of the trench, leaving a thin gate oxide layer exposed near the top of the trench. An angled implant is conducted that implants dopants through the exposed gate oxide and into the side of the trench. If the implanted dopants are n-type, this technique may be used to extend an n+ source region to be below the top of the polysilicon in the trench. If the implanted dopants are p-type, the dopants may be used to form a p-MOS device that turns on when the polysilicon is biased with a negative voltage. P-MOS and n-MOS devices can be formed in a single cell using this technique, where turning on the n-MOS device turns on a vertical power switch, and turning on the p-MOS device turns off the power switch.

A power device is divided into an active area, an active area perimeter, and a termination region. An array of insulated gates formed in trenches form cells in a p-well body, where n+ source regions are formed in the top surface of the silicon wafer and surround the tops of the trenches. A top cathode electrode contacts the source regions, and an anode electrode is on the bottom of the die. A sufficiently high reverse voltage causes a breakdown current to flow between the anode and cathode electrodes. To ensure that a reverse breakdown voltage current occurs away from the gate oxide and/or the termination region, the active area and the active area perimeter of the p-well are additionally doped with p-type dopants to form deep p+ regions in selected areas that extend below the trenches. The deep p+ regions channel the breakdown current away from active cells and the termination region.

An electrostatic discharge (ESD) protection device includes a pad, a diode, a gate ground NMOS (GGNMOS) transistor and a thyristor. The diode includes an anode connected with the pad. The GGNMOS transistor is connected between a cathode of the diode and a ground terminal. The thyristor is formed between the diode and the ground terminal when an ESD current may flow from the pad.

An electrostatic discharge (ESD) protection device includes a pad, a diode, a gate ground NMOS (GGNMOS) transistor and a thyristor. The diode includes an anode connected with the pad. The GGNMOS transistor is connected between a cathode of the diode and a ground terminal. The thyristor is formed between the diode and the ground terminal when an ESD current may flow from the pad.

A bi-directional semiconductor switching device is formed by forming first and second vertical field effect transistors (FETs) formed in tandem from a semiconductor substrate. A source for the first FET is on a first side of the substrate and a source for the second FET is on a second side of the substrate opposite the first side. Gates for both the first and second. FETs are disposed in tandem in a common set of trenches formed a drift region of the semiconductor substrate that is sandwiched between the sources for the first and second FETs. The drift layer acts as a common drain for both the first FET and second FET.