A method of manufacturing a semiconductor integrated circuit includes forming a body region having a second conductivity type in an upper portion of a support layer having a first conductivity type and forming a well region having a second conductivity type in an upper portion of the support layer. An output side buried layer is formed inside the body region and a circuit side buried layer is formed inside the well region. A trench is dug to penetrate through the body region and a control electrode structure is buried in the gate trench. First and second terminal regions are formed on the well region and an output terminal region is formed on the body region. An output stage element having the output terminal region is controlled by a circuit element including the first and second terminal regions.

A method of forming a semiconductor device includes forming a first vertical protection device comprising a thyristor in a substrate, forming a first lateral trigger element for triggering the first vertical protection device in the substrate, and forming an electrical path in the substrate to electrically couple the first lateral trigger element with the first vertical protection device.

A power semiconductor device includes a semiconductor wafer, a thyristor structure, and a bipolar junction transistor. The thyristor structure includes a first emitter layer of a first conductivity type adjacent the first main side, a first base layer of a second conductivity type, a second base layer of the first conductivity type, a second emitter layer of the second conductivity type, a gate electrode, a first main electrode, and a second main electrode arranged. The bipolar junction transistor includes a base electrode electrically separated from the gate electrode, a third main electrode arranged on the first main side and a fourth main electrode arranged on the second main side. The first main electrode is electrically connected to the third main electrode and the second main electrode is electrically connected to the fourth main electrode.

A method of forming a semiconductor device includes forming a first vertical protection device comprising a thyristor in a substrate, forming a first lateral trigger element for triggering the first vertical protection device in the substrate, and forming an electrical path in the substrate to electrically couple the first lateral trigger element with the first vertical protection device.

Protection against electrostatic discharges is to be improved for electronic devices, or is to be provided in the first place. The device for protection against electrostatic discharges having an integrated semiconductor protection device comprises an inner region (1) configured at least as a thyristor (SCR) and at least one outer region (2a, 2b) configured as a corner region, which is formed and configured at least as a PNP transistor. The inner region (1) and the at least one outer region (2a, 2b) are arranged adjacent to one another.

A semiconductor device of the present invention achieves improved avoidance of a parasitic operation in a circuit region while achieving miniaturization of the semiconductor device and a reduction in the amount of time for manufacturing the semiconductor device. The semiconductor device according to the present invention includes an IGBT disposed on a first main surface of a semiconductor substrate provided with a drift layer of a first conductivity type; a thyristor disposed on the first main surface of the semiconductor substrate; a circuit region; a hole-current retrieval region separating the IGBT and the circuit region in a plan view; and a diffusion layer of a second conductivity type, the diffusion layer being disposed on a second main surface of the semiconductor substrate. The IGBT has an effective area equal to or less than an effective area of the thyristor in a plan view.

An insulated gate turn-off (IGTO) device has a PNPN layered structure so that vertical NPN and PNP transistors are formed. Trench gates are formed extending into the intermediate P-layer. The device is formed of an array of cells. A P-channel MOSFET, having a trenched gate, is formed in some of the cells. The control terminal of the IGTO device is connected to the insulated gates of all cells, including to the gate of the P-channel MOSFET, and to the intermediate P-layer. To turn the device on, a positive voltage is applied to the control terminal to turn on the NPN transistor by forward biasing its base-emitter. To turn off the IGTO device, a negative voltage is applied to the control terminal to turn on the P-channel MOSFET to short the NPN base to its emitter.

A bidirectional power semiconductor device with full turn-off control in both current directions and improved electrical and thermal properties is provided, the device comprises a plurality of first gate commutated thyristor (GCT) cells and a plurality of second GCT cells alternating with each other, a first base layer of each first GCT cell is separated from a neighbouring second anode layer of a neighbouring second GCT cell by a first separation region, and a second base layer of each second GCT cell is separated from a neighbouring first anode layer of a neighbouring first GCT cell by a second separation region.

A triac has a vertical structure formed from a silicon substrate having an upper surface side. A main metallization on the upper surface side has a first portion resting on a first region of a first conductivity type formed in a layer of a second conductivity type. A second portion of the main metallization rests on a portion of the layer. A gate metallization on the upper surface side rests on a second region of the first conductivity type formed in the layer in the vicinity of the first region. A porous silicon bar formed in the layer at the upper surface side has a first end in contact with the gate metallization and a second end in contact with the main metallization.

A six-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with methods of operation. Methods of increasing the operational speed in reading the contents of a selected memory cell in an array of such memory cells while lowering power consumption, and of avoiding an indeterminate memory cell state when a memory cell is “awakened” from Standby are described.