In some embodiments, an integrated circuit includes multiple charge storage regions configured to receive charge carriers from a photodetection region in response to a single excitation of a sample. In some embodiments, an integrated circuit includes first and second charge transfer paths configured to electrically couple a photodetection region to first and second charge storage regions, with the second charge transfer path bypassing the first charge storage region. In some embodiments, an integrated circuit includes a photodetection region configured to induce an intrinsic electric field having a vector component in at least three substantially perpendicular directions. In some embodiments, an integrated circuit includes multiple transfer gates configured to control charge carrier transfer out of a photodetection region in different directions. In some embodiments, an integrated circuit includes a photodetection region and multiple transfer gates configured to control charge carrier transfer from the photodetection region to one or more drain regions.

A fabrication method of a layer structure for mounting a semiconductor device is provided, which includes the steps of: providing a base material, wherein the base material has a conductive layer having a first surface having a plurality of first conductive elements and an opposite second surface having a plurality of second conductive elements, and a first encapsulant formed on the first surface of the conductive layer for encapsulating the first conductive elements; partially removing the conductive layer to form a circuit layer that electrically connects the first conductive elements and the second conductive elements; and forming a second encapsulant on a bottom surface of the first encapsulant for encapsulating the circuit layer and the second conductive elements, thus reducing the fabrication difficulty and increasing the product yield.

A fabrication method of a layer structure for mounting a semiconductor device is provided, which includes the steps of: providing a base material, wherein the base material has a conductive layer having a first surface having a plurality of first conductive elements and an opposite second surface having a plurality of second conductive elements, and a first encapsulant formed on the first surface of the conductive layer for encapsulating the first conductive elements; partially removing the conductive layer to form a circuit layer that electrically connects the first conductive elements and the second conductive elements; and forming a second encapsulant on a bottom surface of the first encapsulant for encapsulating the circuit layer and the second conductive elements, thus reducing the fabrication difficulty and increasing the product yield.

An electronic component is formed by a semiconductor component or a semiconductor-like structure having gate electrode assemblies, for reading out the quantum state of a qubit in a quantum dot. The electronic component comprises a substrate having a two-dimensional electron gas or electron hole gas. Electrical contacts connect the gate electrode assemblies to voltage sources. The gate electrode assemblies have gate electrodes, which are arranged on a surface of the electronic component, for producing potential wells in the substrate.

A fabrication method of a layer structure for mounting a semiconductor device is provided, which includes the steps of: providing a base material, wherein the base material has a conductive layer having a first surface having a plurality of first conductive elements and an opposite second surface having a plurality of second conductive elements, and a first encapsulant formed on the first surface of the conductive layer for encapsulating the first conductive elements; partially removing the conductive layer to form a circuit layer that electrically connects the first conductive elements and the second conductive elements; and forming a second encapsulant on a bottom surface of the first encapsulant for encapsulating the circuit layer and the second conductive elements, thus reducing the fabrication difficulty and increasing the product yield.

A fabrication method of a layer structure for mounting a semiconductor device is provided, which includes the steps of: providing a base material, wherein the base material has a conductive layer having a first surface having a plurality of first conductive elements and an opposite second surface having a plurality of second conductive elements, and a first encapsulant formed on the first surface of the conductive layer for encapsulating the first conductive elements; partially removing the conductive layer to form a circuit layer that electrically connects the first conductive elements and the second conductive elements; and forming a second encapsulant on a bottom surface of the first encapsulant for encapsulating the circuit layer and the second conductive elements, thus reducing the fabrication difficulty and increasing the product yield.

An electronic component (10, 110) is designed as a semiconductor or with a semiconductor-like structure for moving a quantum dot (68, 168) over a distance. The electronic component (10, 110) comprises a substrate (32, 132) having a two-dimensional electron gas or electron hole gas. A gate electrode assembly (16, 18, 20, 116, 118, 120) having gate electrodes (38, 40, 42, 44, 138, 140, 142, 144) is arranged on a surface (31, 131) of the electronic component (10, 110). The gate electrode assembly (16, 18, 20, 116, 118, 120) produces a potential well (66, 166) in the substrate (32, 132). Electrical terminals for connecting the gate electrode assembly (16, 18, 20, 116, 118, 120) to voltage sources are provided for this purpose. The disclosure further relates to a method for such an electronic component (10, 110).

An electronic component (10, 110) is designed as a semiconductor or with a semiconductor-like structure for moving a quantum dot (68, 168) over a distance. The electronic component (10, 110) comprises a substrate (32, 132) having a two-dimensional electron gas or electron hole gas. A gate electrode assembly (16, 18, 20, 116, 118, 120) having gate electrodes (38, 40, 42, 44, 138, 140, 142, 144) is arranged on a surface (31, 131) of the electronic component (10, 110). The gate electrode assembly (16, 18, 20, 116, 118, 120) produces a potential well (66, 166) in the substrate (32, 132). Electrical terminals for connecting the gate electrode assembly (16, 18, 20, 116, 118, 120) to voltage sources are provided for this purpose. The disclosure further relates to a method for such an electronic component (10, 110).

Provided is a charge-transfer-type sensor suitable for high integration while eliminating a potential barrier. A sensor provided with a semiconductor substrate 10 partitioned into a sensing region 5 in which a potential varies in corresponding fashion to a variation in the external environment, a charge input region 2 for supplying charges to the sensing region 5, an input charge control region 3 interposed between the sensing region 5 and the charge input region 2, and a charge accumulation region 7 for accumulating electric charges transported from the sensing region 5, the sensor for detecting the amount of electric charges accumulated in the charge accumulation region 7, wherein a diffusion layer 4 is formed between the input charge control region 3 and the sensing region 5 of the substrate 10, and dopants for producing charges having the same polarity as the charges supplied from the charge input region 2 are diffused in the diffusion layer 4.

A fabrication method of a layer structure for mounting a semiconductor device is provided, which includes the steps of: providing a base material, wherein the base material has a conductive layer having a first surface having a plurality of first conductive elements and an opposite second surface having a plurality of second conductive elements, and a first encapsulant formed on the first surface of the conductive layer for encapsulating the first conductive elements; partially removing the conductive layer to form a circuit layer that electrically connects the first conductive elements and the second conductive elements; and forming a second encapsulant on a bottom surface of the first encapsulant for encapsulating the circuit layer and the second conductive elements, thus reducing the fabrication difficulty and increasing the product yield.